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| 型號： | EVAL-AD7734EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 21/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD7734 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 15.4k |
| 數(shù)據(jù)接口： | 串行 |
| 輸入范圍： | ±10 V |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | 85mW @ 5V |
| 工作溫度： | -40°C ~ 105°C |
| 已用 IC / 零件： | AD7734 |
| 已供物品： | 板，纜線，CD |
| 產(chǎn)品目錄頁面： | 779 (CN2011-ZH PDF) |
| 相關(guān)產(chǎn)品： | AD7734BRUZ-REEL7TR-ND - IC ADC 24BIT 4CH SIG-DEL 28TSSOP AD7734BRUZ-REEL-ND - IC ADC 24BIT 4CH SIG-DEL 28TSSOP AD7734BRUZ-ND - IC ADC 24BIT 4-CH 28-TSSOP AD7734BRU-ND - IC ADC 24BIT 4-CH 28-TSSOP |
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AD7734
Data Sheet
Rev. A | Page 28 of 32
MULTIPLEXER, CONVERSION, AND DATA OUTPUT TIMING
The specified conversion time includes one or two settling and
sampling periods and a scaling time.
With chopping enabled (Figure 25), a conversion cycle starts
with a settling time of 43 MCLK cycles or 44 MCLK cycles
(~7 s with a 6.144 MHz MCLK) to allow the circuits following
the multiplexer to settle. The sigma-delta modulator then
samples the analog signals and the digital filter processes the
digital data stream. The sampling time depends on FW, i.e., on
the channel conversion time register contents. After another
settling of 42 MCLK cycles (~6.8 s), the sampling time is
repeated with a reversed (chopped) analog input signal. Then,
during the scaling time of 163 MCLK cycles (~26.5 s), the two
results from the digital filter are averaged, scaled using the
calibration registers, and written into the channel data register.
With chopping disabled (Figure 26), there is only one sampling
time preceded by a settling time of 43 MCLK cycles or
44 MCLK cycles and followed by a scaling time of
163 MCLK cycles.
The RDY pin goes high during the scaling time, regardless of its
previous state. The relevant RDY bit is set in the ADC status
register and in the channel status register, and the RDY pin goes
low when the channel data register is updated and the channel
conversion cycle is finished. If in continuous conversion mode,
the part will automatically continue with a conversion cycle on
the next enabled channel.
Note that every channel can be configured independently for
conversion time and chopping mode. The overall cycle and
effective per channel data rates depend on all enabled
channel settings.
SIGMA-DELTA ADC
The AD7734 core consists of a charge balancing sigma-delta
modulator and a digital filter. The architecture is optimized for
fast, fully settled conversion. This allows for fast channel-to-
channel switching while maintaining inherently excellent
linearity, high resolution, and low noise.
– CHANNEL 1
SCALING
TIME
SAMPLING
TIME
+ CHANNEL 1
SAMPLING
TIME
SETTLING
TIME
MULTIPLEXER
– CHANNEL 0
RDY
SETTLING
TIME
CONVERSION TIME
Figure 25. Multiplexer and Conversion Timing—Continuous Conversion on Several Channels with Chopping Enabled
SCALING
TIME
CHANNEL 1
SAMPLING
TIME
MULTIPLEXER
CHANNEL 0
RDY
SETTLING
TIME
CONVERSION TIME
Figure 26. Multiplexer and Conversion Timing—Continuous Conversion on Several Channels with Chopping Disabled
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