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參數(shù)資料
| 型號(hào)： | EVAL-AD7715-3EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 5/40頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD7715 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 500 |
| 數(shù)據(jù)接口： | 串行 |
| 輸入范圍： | ±VREF/增益 |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | 5.3mW @ 3.3 V |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7715-3 |
| 已供物品： | 板，CD |
| 相關(guān)產(chǎn)品： | AD7715ARUZ-5-ND - IC ADC 16BIT SIGMA-DELTA 16TSSOP AD7715ARUZ-3-ND - IC ADC 16BIT SIGMA-DELTA 16TSSOP AD7715ANZ-3-ND - IC ADC 16BIT SIGMA-DELTA 16DIP AD7715ARUZ-5REEL7-ND - IC ADC 16BIT SIGMA-DELTA 16TSSOP AD7715ARUZ-3REEL7-ND - IC ADC 16BIT SIGMA-DELTA 16TSSOP AD7715ARZ-3REEL-ND - IC ADC 16BIT SIGMA-DELTA 16SOIC AD7715ARZ-3-ND - IC ADC 16BIT 3V 16-SOIC AD7715ANZ-5-ND - IC ADC 16BIT 5V 16-DIP AD7715ARZ-5REEL-ND - IC ADC 16BIT 5V 16-SOIC AD7715ARZ-5-ND - IC ADC 16BIT SIGMA-DELTA 16-SOIC 更多... |
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AD7715
Rev. D | Page 13 of 40
COMMUNICATIONS REGISTER (RS1, RS0 = 0, 0)
The communications register is an eight-bit register from which data can either be read or to which data can be written. All communica-
tions to the part must start with a write operation to the communications register. The data written to the communications register
determines whether the next operation is a read or write operation and to which register this operation takes place. Once the subsequent
read or write operation to the selected register is complete, the interface returns to where it expects a write operation to the communications
register. This is the default state of the interface, and on power-up or after a reset, the AD7715 is in this default state waiting for a write
operation to the communications register. In situations where the interface sequence is lost, if a write operation to the device of sufficient
duration (containing at least 32 serial clock cycles) takes place with DIN high, the AD7715 returns to this default state. Table 7 outlines
the bit designations for the communications register.
Table 7. Communications Register
0/DRDY
ZERO
RS1
RS0
R/W
STBY
G1
G0
Table 8.
Bit Name
Description
0/DRDY
For a write operation, a 0 must be written to this bit so that the write operation to the communications register actually takes
place. If a 1 is written to this bit, the part will not clock on to subsequent bits in the register. Instead, it stays at this bit location
until a 0 is written to this bit. Once a 0 is written to this bit, the next 7 bits are loaded to the communications register. For a read
operation, this bit provides the status of the DRDY flag from the part. The status of this bit is the same as the DRDY output pin.
ZERO
For a write operation, a 0 must be written to this bit for correct operation of the part. Failure to do this results in unspecified
operation of the device. For a read operation, a 0 is read back from this bit location.
RS1, RS0
Register Selection Bits. These bits select to which one of four on-chip registers the next read or write operation takes place as
shown in Table 9 along with the register size. When the read or write to the selected register is complete, the part returns to
where it is waiting for a write operation to the Communications Register. It does not remain in a state where it continues to
access the selected register.
R/W
Read/Write Select. This bit selects whether the next operation
is a read or write operation to the selected register. A 0 indicates a write cycle as the next operation to the appropriate register,
while a 1 indicates a read operation from the appropriate register.
STBY
Standby. Writing a 1 to this bit puts the part in its standby or power-down mode. In this mode, the part consumes only
10 μA of power supply current. The part retains its calibration and control word information when in STANDBY. Writing a 0 to
this bit places the part in its normal operating mode. The default value for this bit after power-on or RESET is 0.
G1, G0
Gain Select bits. See Table 10.
Table 9. Register Section
RS1
RS0
Register
Register Size
0
Communications register
8 bits
0
1
Setup register
8 bits
1
0
Test register
8 bits
1
Data register
16 bits
Table 10.
G2
G1
Gain Setting
0
1
0
1
2
1
32
1
128
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