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| 型號(hào)： | EVAL-AD7715-3EBZ |
| 廠(chǎng)商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 10/40頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD7715 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 500 |
| 數(shù)據(jù)接口： | 串行 |
| 輸入范圍： | ±VREF/增益 |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | 5.3mW @ 3.3 V |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7715-3 |
| 已供物品： | 板，CD |
| 相關(guān)產(chǎn)品： | AD7715ARUZ-5-ND - IC ADC 16BIT SIGMA-DELTA 16TSSOP AD7715ARUZ-3-ND - IC ADC 16BIT SIGMA-DELTA 16TSSOP AD7715ANZ-3-ND - IC ADC 16BIT SIGMA-DELTA 16DIP AD7715ARUZ-5REEL7-ND - IC ADC 16BIT SIGMA-DELTA 16TSSOP AD7715ARUZ-3REEL7-ND - IC ADC 16BIT SIGMA-DELTA 16TSSOP AD7715ARZ-3REEL-ND - IC ADC 16BIT SIGMA-DELTA 16SOIC AD7715ARZ-3-ND - IC ADC 16BIT 3V 16-SOIC AD7715ANZ-5-ND - IC ADC 16BIT 5V 16-DIP AD7715ARZ-5REEL-ND - IC ADC 16BIT 5V 16-SOIC AD7715ARZ-5-ND - IC ADC 16BIT SIGMA-DELTA 16-SOIC 更多... |
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AD7715
Rev. D | Page 18 of 40
CALIBRATION SEQUENCES
The AD7715 contains a number of calibration options as
the operations involved and the duration of the operations.
There are two methods of determining the end of calibration.
The first is to monitor when DRDY returns low at the end of
the sequence. DRDY not only indicates when the sequence is
complete but also that the part has a valid new sample in its
data register. This valid new sample is the result of a normal
conversion which follows the calibration sequence. The second
method of determining when calibration is complete is to
monitor the MD1 and MD0 bits of the setup register. When
these bits return to 0, 0 following a calibration command, it
indicates that the calibration sequence is complete. This method
does not give any indication of there being a valid new result in
the data register. However, it gives an earlier indication than
DRDY that calibration is complete. The duration to when the
mode bits (MD1 and MD0) return to 0, 0 represents the
duration of the calibration carried out. The sequence to when
DRDY goes low also includes a normal conversion and a
pipeline delay, tP, to correctly scale the results of this first
conversion. tP will never exceed 2000 × tCLK IN. The time for both
methods is given in
.
Table 23. Calibration Sequences
Calibration Type
MD1, MD0
Calibration Sequence
Duration to Mode Bits
Duration to DRDY
Self Calibration
0, 1
Internal ZS Cal @ Selected Gain +
6 × 1/Output Rate
9 ×1/Output Rate + tP
Internal FS Cal @ Selected Gain
ZS System Calibration
1, 0
ZS Cal on AIN @ Selected Gain
3 × 1/Output Rate
4 × 1/Output Rate + tP
FS System Calibration
1, 1
FS Cal on AIN @ Selected Gain
3 × 1/Output Rate
4 × 1/Output Rate + tP
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