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參數(shù)資料
| 型號(hào)： | EVAL-AD7715-3EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 39/40頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD7715 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 500 |
| 數(shù)據(jù)接口： | 串行 |
| 輸入范圍： | ±VREF/增益 |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | 5.3mW @ 3.3 V |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7715-3 |
| 已供物品： | 板，CD |
| 相關(guān)產(chǎn)品： | AD7715ARUZ-5-ND - IC ADC 16BIT SIGMA-DELTA 16TSSOP AD7715ARUZ-3-ND - IC ADC 16BIT SIGMA-DELTA 16TSSOP AD7715ANZ-3-ND - IC ADC 16BIT SIGMA-DELTA 16DIP AD7715ARUZ-5REEL7-ND - IC ADC 16BIT SIGMA-DELTA 16TSSOP AD7715ARUZ-3REEL7-ND - IC ADC 16BIT SIGMA-DELTA 16TSSOP AD7715ARZ-3REEL-ND - IC ADC 16BIT SIGMA-DELTA 16SOIC AD7715ARZ-3-ND - IC ADC 16BIT 3V 16-SOIC AD7715ANZ-5-ND - IC ADC 16BIT 5V 16-DIP AD7715ARZ-5REEL-ND - IC ADC 16BIT 5V 16-SOIC AD7715ARZ-5-ND - IC ADC 16BIT SIGMA-DELTA 16-SOIC 更多... |
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AD7715
Rev. D | Page 8 of 40
TIMING CHARACTERISTICS
DVDD = 3 V to 5.25 V; AVDD = 3 V to 5.25 V; AGND = DGND = 0 V; fCLKIN = 2.4576 MHz; Input Logic 0 = 0 V, Logic 1 = DVDD, unless
otherwise noted.
Table 4.
Limit at TMIN, TMAX
(A Version)
Unit
Conditions/Comments
400
kHz min
2.5
MHz max
Master clock frequency: crystal oscillator or externally supplied for specified
performance
tCLK IN LO
0.4 × tCLK IN
ns min
Master clock input low time; tCLK IN = 1/fCLK IN
tCLK IN HI
0.4 × tCLK IN
ns min
Master clock input high time
t1
500 × tCLK IN
ns nom
DRDY high time
t2
100
ns min
RESET pulsewidth
Read Operation
t3
0
ns min
DRDY to CS setup time
t4
120
ns min
CS falling edge to SCLK rising edge setup time
t55
0
ns min
SCLK falling edge to data valid delay
80
ns max
DVDD = 5 V
100
ns max
DVDD = 3.3 V
t6
100
ns min
SCLK high pulsewidth
t7
100
ns min
SCLK low pulsewidth
t8
0
ns min
CS rising edge to SCLK rising edge hold time
t96
10
ns min
Bus relinquish time after SCLK rising edge
60
ns max
DVDD = +5 V
100
ns max
DVDD = +3.3 V
t10
100
ns max
SCLK falling edge to DRDY high7
Write Operation
t11
120
ns min
CS falling edge to SCLK rising edge setup time
t12
30
ns min
Data valid to SCLK rising edge setup time
t13
20
ns min
Data valid to SCLK rising edge hold time
t14
100
ns min
SCLK high pulsewidth
t15
100
ns min
SCLK low pulsewidth
t16
0
ns min
CS rising edge to SCLK rising edge hold time
1 Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V.
2 See Figure 8 and Figure 9.
3 CLKIN Duty Cycle range is 45% to 55%. CLKIN must be supplied whenever the AD7715 is not in standby mode. If no clock is present in this case, the device can draw
higher current than specified and possibly become uncalibrated.
4 The AD7715 is production tested with fCLKIN at 2.4576 MHz (1 MHz for some IDD tests). It is guaranteed by characterization to operate at 400 kHz.
5 These numbers are measured with the load circuit of Figure 2 and defined as the time required for the output to cross the VOL or VOH limits.
6 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then
extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.
7
DRDY returns high after the first read from the device after an output update. The same data can be read again, if required, while DRDY is high although take care that
subsequent reads do not occur close to the next output update.
TO
OUTPUT
PIN
+1.6V
ISINK (800A AT DVDD = 5V
100A AT DVDD = 3.3V)
ISOURCE (200A AT DVDD = 5V
100A AT DVDD = 3.3V)
50pF
08
51
9-
00
2
Figure 2. Load Circuit for Access Time and Bus Relinquish Time
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