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參數(shù)資料
| 型號： | EVAL-AD7654CBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD7654 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | PulSAR® |
| ADC 的數(shù)量： | 2 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 500k |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 輸入范圍： | 0 ~ 5 V |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | 120mW @ 500kSPS |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7654 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | AD7654ACPZ-ND - IC ADC 16BIT DUAL 2CH 48-LFCSP AD7654ASTZRL-ND - IC ADC 16BIT DUAL 2CH 48LQFP AD7654ACPZRL-ND - IC ADC 16BIT DUAL 2CH 48LFCSP AD7654ASTZ-ND - IC ADC 16BIT 500KSPS DUAL 48LQFP |
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AD7654
Rev. B | Page 20 of 28
SERIAL INTERFACE
The AD7654 is configured to use the serial interface when the
SER/PAR is held high. The AD7654 outputs 32 bits of data,
MSB first, on the SDOUT pin. The order of the channels being
output is also controlled by A/B. When high, Channel A is
output first; when low, Channel B is output first. This data
is synchronized with the 32 clock pulses provided on the
SCLK pin.
MASTER SERIAL INTERFACE
Internal Clock
The AD7654 is configured to generate and provide the serial
data clock SCLK when the EXT/INT pin is held low. The
AD7654 also generates a SYNC signal to indicate to the host
when the serial data is valid. The serial clock SCLK and the
SYNC signal can be inverted if desired. The output data is valid
on both the rising and falling edge of the data clock. Depending
on RDC/SDIN input, the data can be read after each conversion
show the detailed timing diagrams of these two modes.
Usually, because the AD7654 is used with a fast throughput, the
master-read-during-convert mode is the most recommended
serial mode when it can be used. In this mode, the serial clock
and data toggle at appropriate instants, which minimizes
potential feedthrough between digital activity and the critical
conversion decisions. The SYNC signal goes low after the LSB
of each channel has been output. Note that in this mode, the
SCLK period changes because the LSBs require more time to
settle, and the SCLK is derived from the SAR conversion clock.
other modes, the signal BUSY returns low after the 32 data bits
are pulsed out and not at the end of the conversion phase,
which results in a longer BUSY width. One advantage of using
this mode is that it can accommodate slow digital hosts because
the serial clock can be slowed down by using DIVSCLK[1:0]
inputs. Refer to Table 4 for the timing details.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EVAL-AD7655CB | 制造商:Analog Devices 功能描述:Evaluation Board For The 48 Lead Pulsar Analog To Digital Converter Family 制造商:Rochester Electronics LLC 功能描述:EVAL BRD LOW COST 4-CH 1 MSPS 16-BIT ADC - Bulk |
| EVAL-AD7655CBZ | 功能描述:BOARD EVALUATION FOR AD7655 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:PulSAR® 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標(biāo)準(zhǔn)）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
| EVAL-AD7655EDZ | 功能描述:BOARD EVAL FOR AD7655 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:* 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標(biāo)準(zhǔn)）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
| EVAL-AD7656-1CBZ | 功能描述:BOARD EVAL FOR AD7656-1 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:iCMOS® 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標(biāo)準(zhǔn)）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
| EVAL-AD7656-1EDZ | 功能描述:BOARD EVAL CONTROL AD7656-1 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:iCMOS® 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標(biāo)準(zhǔn)）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
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