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參數(shù)資料
| 型號： | EVAL-AD7653CBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 16/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD7653 |
| 標準包裝： | 1 |
| 系列： | PulSAR® |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 1M |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 輸入范圍： | 0 ~ 2.5 V |
| 在以下條件下的電源（標準）： | 92mW @ 666kSPS |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7653 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | AD7653ACPZ-ND - IC ADC 16BIT UNIPOLAR 48LFCSP AD7653ACPZRL-ND - IC ADC 16BIT UNIPOLAR 48LFCSP AD7653ASTZRL-ND - IC ADC 16BIT UNIPOLAR 48LQFP AD7653ASTZ-ND - IC ADC 16BIT 1MSPS W/REF 48-LQFP |
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AD7653
External Discontinuous Clock Data Read After
Conversion
External Clock Data Read During Conversion
Figure 35 shows the detailed timing diagrams of this method.
During a conversion, while both CS and RD are both LOW, the
result of the previous conversion can be read. The data is shifted
out MSB first with 16 clock pulses, and is valid on both the
rising and falling edges of the clock. The 16 bits must be read
before the current conversion is complete; otherwise,
RDERROR is pulsed HIGH and can be used to interrupt the
host interface to prevent incomplete data reading. There is no
daisy-chain feature in this mode, and the RDC/SDIN input
should always be tied either HIGH or LOW.
Though the maximum throughput cannot be achieved using
this mode, it is the most recommended of the serial slave modes.
shows the detailed timing diagrams of this method.
After a conversion is complete, indicated by BUSY returning
LOW, the conversion’s result can be read while both CS and RD
are LOW. Data is shifted out MSB first with 16 clock pulses and
is valid on the rising and falling edges of the clock.
Among the advantages of this method is the fact that conversion
performance is not degraded because there are no voltage
transients on the digital interface during the conversion process.
Another advantage is the ability to read the data at any speed up
to 40 MHz, which accommodates both the slow digital host
interface and the fastest serial reading.
To reduce performance degradation due to digital activity, a fast
discontinuous clock (at least 18 MHz when Impulse mode is
used, 25 MHz when Normal mode is used, or 40 MHz when
Warp mode is used) is recommended to ensure that all the bits
are read during the first half of the conversion phase. It is also
possible to begin to read data after conversion and continue to
read the last bits after a new conversion has been initiated. This
allows the use of a slower clock speed like 14 MHz in Impulse
mode, 18 MHz in Normal mode, and 25 MHz in Warp mode.
Finally, in this mode only, the AD7653 provides a daisy-chain
feature using the RDC/SDIN pin for cascading multiple
converters together. This feature is useful for reducing compo-
nent count and wiring connections when desired, as, for
instance, in isolated multiconverter applications.
The concatenation of two devices is shown in
Simultaneous sampling is possible by using a common CNVST
signal. It should be noted that the RDC/SDIN input is latched
on the edge of SCLK opposite the one used to shift out the data
on SDOUT. Thus, the MSB of the upstream converter follows
the LSB of the downstream converter on the next SCLK cycle.
Figure 36. Two AD7653s in a Daisy-Chain Configuration
SCLK
SDOUT
RDC/SDIN
BUSY
DATA
OUT
AD7653
#1
(DOWNSTREAM)
BUSY
OUT
SCLK
AD7653
#2
(UPSTREAM)
RDC/SDIN
SDOUT
SCLK IN
CNVST IN
02966-0-019
CNVST
CS
CNVST
CS
CS IN
Rev. A | Page 23 of 28
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EVAL-AD7653EDZ | 功能描述:BOARD EVAL FOR AD7653 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:* 產(chǎn)品培訓模塊:Obsolescence Mitigation Program 標準包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標準）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
| EVAL-AD7654CB | 制造商:Analog Devices 功能描述: |
| EVAL-AD7654CBZ | 功能描述:BOARD EVALUATION FOR AD7654 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:PulSAR® 產(chǎn)品培訓模塊:Obsolescence Mitigation Program 標準包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標準）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
| EVAL-AD7655CB | 制造商:Analog Devices 功能描述:Evaluation Board For The 48 Lead Pulsar Analog To Digital Converter Family 制造商:Rochester Electronics LLC 功能描述:EVAL BRD LOW COST 4-CH 1 MSPS 16-BIT ADC - Bulk |
| EVAL-AD7655CBZ | 功能描述:BOARD EVALUATION FOR AD7655 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:PulSAR® 產(chǎn)品培訓模塊:Obsolescence Mitigation Program 標準包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標準）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
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