AVCC = 4.75 V to 5.25 V, C
參數(shù)資料
型號： EVAL-AD7264EDZ
廠商： Analog Devices Inc
文件頁數(shù)： 24/29頁
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR AD7264
標準包裝： 1
ADC 的數(shù)量： 1
位數(shù)： 14
采樣率（每秒）： 1M
數(shù)據(jù)接口： 串行
輸入范圍： 5 Vpp
在以下條件下的電源（標準）： 120mW @ 1MSPS
工作溫度： -40°C ~ 105°C
已用 IC / 零件： AD7264
已供物品： 板
Data Sheet
AD7264
Rev. B | Page 3 of 28
SPECIFICATIONS
AVCC = 4.75 V to 5.25 V, CA_CBVCC = CC_CDVCC = 2.7 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, fS = 1 MSPS and fSCLK = 34 MHz for the
AD7264, fS = 500 kSPS and fSCLK = 20 MHz for the AD7264-5, VREF = 2.5 V internal/external; TA = 40°C to +105°C, unless otherwise noted.
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE1
f
IN = 100 kHz sine wave
Signal-to-Noise Ratio (SNR)2
76
78
dB
PGA gain setting = 2
Signal-to-(Noise + Distortion) Ratio
(SINAD)2
74
77
dB
Total Harmonic Distortion (THD)2
85
77
dB
Spurious-Free Dynamic Range (SFDR)
97
dB
Common-Mode Rejection Ratio (CMRR)
76
dB
For PGA gain setting = 2, ripple
frequency of 50 Hz/60 Hz; see
ADC-to-ADC Isolation2
90
dB
Bandwidth3
1.2
MHz
@ 3 dB; PGA gain setting = 128
1.7
MHz
@ 3 dB; PGA gain setting = 2
DC ACCURACY
Resolution
14
Bits
Integral Nonlinearity2
±1.5
±3
LSB
Differential Nonlinearity2
±0.5
±0.99
LSB
Guaranteed no missed codes to 14 bits
Positive Full-Scale Error2
±0.122
±0.305
% FSR
Precalibration
±0.018
% FSR
Postcalibration
Positive Full-Scale Error Match2
±0.061
% FSR
Zero Code Error2
±0.092
±0.244
% FSR
Precalibration
±0.012
% FSR
Postcalibration
Zero Code Error Match2
±0.061
% FSR
Negative Full-Scale Error2
±0.122
±0.305
% FSR
Precalibration
±0.018
% FSR
Postcalibration
Negative Full-Scale Error Match2
±0.061
% FSR
Zero Code Error Drift
2.5
V/°C
ANALOG INPUT
Input Voltage Range, V
IN+ and VIN
Gain
2
V
REF
CM
×
±
V
CM = AVCC/2; PGA gain setting ≥ 2
Common-Mode Voltage Range, V
CM
V
CM 100 mV
V
CM + 100 mV
V
CM = 2 V; PGA gain setting = 1;
(V
CC/2) 0.4
(V
CC/2) + 0.2
V
CM = AVCC/2; PGA gain setting = 2
(V
CC/2) 0.4
(V
CC/2) + 0.4
V
CM = AVCC/2; 3 ≤ PGA gain setting ≤ 32
(V
CC/2) 0.6
(V
CC/2) + 0.8
V
CM = AVCC/2; PGA gain setting ≥ 48
DC Leakage Current
±0.001
±1
A
Input Capacitance3
5
pF
Input Impedance3
1
GΩ
REFERENCE INPUT/OUTPUT
Reference Output Voltage5
2.495
2.5
2.505
V
2.5 V ± 5 mV max @ 25°C
Reference Input Voltage
2.5
V
DC Leakage Current
±0.3
±1
A
External reference applied to
Pin V
REFA/Pin VREFB
Input Capacitance3
20
pF
V
REFA, VREFB Output Impedance
4
Ω
Reference Temperature Coefficient
20
ppm/°C
V
REF Noise
20
V rms
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