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參數(shù)資料
| 型號(hào)： | EVAL-AD5680EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 3/20頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD5680 |
| 產(chǎn)品培訓(xùn)模塊： | DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | nanoDAC™ |
| DAC 的數(shù)量： | 1 |
| 位數(shù)： | 18 |
| 采樣率（每秒）： | 12.5k |
| 數(shù)據(jù)接口： | 串行 |
| 設(shè)置時(shí)間： | 80µs |
| DAC 型： | 電壓 |
| 工作溫度： | -40°C ~ 105°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | AD5680 |
| 相關(guān)產(chǎn)品： | AD5680BRJZ-1500RL7DKR-ND - IC DAC 18BIT 5V SOT23-8 AD5680BRJZ-1500RL7CT-ND - IC DAC 18BIT 5V SOT23-8 AD5680BRJZ-2REEL7DKR-ND - IC DAC 18BIT 5V SOT23-8 AD5680BRJZ-2REEL7CT-ND - IC DAC 18BIT 5V SOT23-8 AD5680BRJZ-2REEL7TR-ND - IC DAC 18BIT 5V SOT23-8 AD5680BRJZ-2500RL7TR-ND - IC DAC 18BIT 5V SOT23-8 AD5680BRJZ-1500RL7TR-ND - IC DAC 18BIT 5V SOT23-8 |
Data Sheet
AD5680
Rev. B | Page 11 of 20
THEORY OF OPERATION
DAC SECTION
The AD5680 DAC is fabricated on a CMOS process. The
architecture consists of a string DAC followed by an output
buffer amplifier. Figure 23 shows a block diagram of the DAC
architecture.
VDD
R
VOUT
GND
RESISTOR
STRING
REF (+)
REF (–)
OUTPUT
AMPLIFIER
05
85
4-
0
3
0
VFB
DAC REGISTER
Figure 23. DAC Architecture
Because the input coding to the DAC is straight binary, the ideal
output voltage is given by
262,144
D
V
REF
OUT
where D is the decimal equivalent of the binary code that is
loaded to the DAC register. It can range from 0 to 262,143.
RESISTOR STRING
The resistor string section is shown in Figure 24. It is simply a
string of resistors, each of value R. The code loaded to the DAC
register determines at which node on the string the voltage is
tapped off to be fed into the output amplifier. The voltage is
tapped off by closing one of the switches connecting the string
to the amplifier. Because it is a string of resistors, it is guaranteed
monotonic.
R
TO OUTPUT
AMPLIFIER
05
85
4-
03
1
Figure 24. Resistor String
OUTPUT AMPLIFIER
The output buffer amplifier can generate rail-to-rail voltages on
its output, which gives an output range of 0 V to VDD. This output
buffer amplifier has a gain of 2 derived from a 50 kΩ resistor
divider network in the feedback path. The output amplifier’s
inverting input is available to the user, allowing for remote
sensing. This VFB pin must be connected to VOUT for normal
operation. It can drive a load of 2 kΩ in parallel with 1000 pF to
GND. The source and sink capabilities of the output amplifier can
be seen in Figure 10. The slew rate is 1.5 V/μs with a to
full-scale settling time of 10 μs.
INTERPOLATOR ARCHITECTURE
The AD5680 contains a 16-bit DAC with an internal clock
generator and interpolator. The voltage levels generated by the
16-bit, 1 LSB step can be subdivided using the interpolator to
increase the resolution to 18 bits.
The 18-bit input code can be divided into two segments:
16-bit DAC code (DB19 to DB4) and 2-bit interpolator code
(DB3 and DB2). The input to the DAC is switched between a
16-bit code (for example, Code 1023) and a 16-bit code + 1 LSB
(for example, Code 1024). The 2-bit interpolator code deter-
mines the duty cycle of the switching and hence the 18-bit
code level. See Table 5 for an example.
Table 5.
18-Bit Code
16-Bit
DAC Code
2-Bit
Interpolator Code
Duty
Cycle
DB19 to DB2
DB19 to DB4
DB3
DB2
4092
1023
0
4093
1023
0
1
25%
4094
1023
1
0
50%
4095
1023
1
75%
4096
1024
0
The DAC output voltage is given by the average value of
the waveform switching between 16-bit code (C) and 16-bit
code + 1 (C + 1). The output voltage is a function of the duty
cycle of the switching.
05854-
032
C
2
16
18
+1
C
PLANT
DAC
VOUT
FILTER
18-BIT INPUT CODE
MUX
C + 1
CLK
INTERPOLATOR
75% DUTY CYCLE
50% DUTY CYCLE
25% DUTY CYCLE
C + 1
Figure 25. Interpolation Architecture
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