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參數(shù)資料
| 型號(hào)： | EVAL-AD5680EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 17/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD5680 |
| 產(chǎn)品培訓(xùn)模塊： | DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | nanoDAC™ |
| DAC 的數(shù)量： | 1 |
| 位數(shù)： | 18 |
| 采樣率（每秒）： | 12.5k |
| 數(shù)據(jù)接口： | 串行 |
| 設(shè)置時(shí)間： | 80µs |
| DAC 型： | 電壓 |
| 工作溫度： | -40°C ~ 105°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | AD5680 |
| 相關(guān)產(chǎn)品： | AD5680BRJZ-1500RL7DKR-ND - IC DAC 18BIT 5V SOT23-8 AD5680BRJZ-1500RL7CT-ND - IC DAC 18BIT 5V SOT23-8 AD5680BRJZ-2REEL7DKR-ND - IC DAC 18BIT 5V SOT23-8 AD5680BRJZ-2REEL7CT-ND - IC DAC 18BIT 5V SOT23-8 AD5680BRJZ-2REEL7TR-ND - IC DAC 18BIT 5V SOT23-8 AD5680BRJZ-2500RL7TR-ND - IC DAC 18BIT 5V SOT23-8 AD5680BRJZ-1500RL7TR-ND - IC DAC 18BIT 5V SOT23-8 |
AD5680
Data Sheet
Rev. B | Page 6 of 20
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
VDD 1
VREF
2
VFB 3
VOUT 4
GND
8
DIN
7
SCLK
6
SYNC
5
AD5680
TOP VIEW
(Not to Scale)
0585
4-
003
Figure 3. 8-Lead SOT-23 Pin Configuration
1
VDD
2
VREF
3
VFB
4
VOUT
8GND
7DIN
6SCLK
5 SYNC
0
585
4-
10
4
AD5680
TOP VIEW
(Not to Scale)
Figure 4. 8-Lead LFCSP Pin Configuration
Table 4. 8-Lead SOT-23 and 8-Lead LFSCP Pin Function Descriptions
Pin No.
Mnemonic
Description
1
VDD
Power Supply Input. The part can be operated from 4.5 V to 5.5 V. VDD should be decoupled to GND.
2
VREF
Reference Voltage Input.
3
VFB
Feedback Connection for the Output Amplifier. VFB should be connected to VOUT for normal operation.
4
VOUT
Analog Output Voltage from DAC. The output amplifier has rail-to-rail operation.
5
SYNC
Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When SYNC
goes low, it enables the input shift register and data is transferred in on the falling edges of the following clocks.
The DAC is updated following the 24th clock cycle unless SYNC is taken high before this edge, in which case the
rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC. SYNC
6
SCLK
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can
be transferred at rates up to 30 MHz.
7
DIN
Serial Data Input. This device has a 24-bit shift register. Data is clocked into the register on the falling edge of the
serial clock input.
8
GND
Ground. Ground reference point for all circuitry on the part.
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