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參數(shù)資料
| 型號： | EVAL-AD5380EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 26/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD5380 |
| 產(chǎn)品培訓模塊： | DAC Architectures |
| 標準包裝： | 1 |
| DAC 的數(shù)量： | 40 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 125k |
| 數(shù)據(jù)接口： | DSP，I²C，MICROWIRE?，并行，QSPI?，SPI? |
| 設置時間： | 8µs |
| DAC 型： | 電壓 |
| 工作溫度： | -40°C ~ 85°C |
| 已供物品： | 板，CD |
| 已用 IC / 零件： | AD5380 |
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AD5380
Data Sheet
Rev. C | Page 32 of 40
AD5380 to PIC16C6x/7x
The PIC16C6x/7x synchronous serial port (SSP) is configured
as an SPI master with the Clock Polarity bit = 0. This is done
by writing to the synchronous serial port control register
(SSPCON). See the PIC16/17 Microcontroller User Manual.
In this example, I/O, port RA1, is being used to pulse SYNC
and enable the serial port of the AD5380. This microcontroller
transfers only eight bits of data during each serial transfer
operation; therefore, three consecutive read/write operations
may be needed depending on the mode. Figure 36 shows the
connection diagram.
03731-036
PIC16C6X/7X
AD5380
SDI/RC4
SDO/RC5
SCK/RC3
RA1
SDO
RESET
SER/PAR
DIN
SCLK
SYNC
SPI/I2C
DVDD
Figure 36. AD5380-to-PIC16C6x/7x Interface
AD5380 to 8051
The AD5380 requires a clock synchronized to the serial data.
Therefore, the 8051 serial interface must be operated in Mode 0.
In this mode, serial data enters and exits through RxD, and a
shift clock is output on TxD. Figure 37 shows how the 8051 is
connected to the AD5380. Because the AD5380 shifts data out
on the rising edge of the shift clock and latches data in on the
falling edge, the shift clock must be inverted. The AD5380
requires its data to be MSB first. Since the 8051 outputs the
LSB first, the transmit routine must take this into account.
03731-037
8XC51
AD5380
RxD
TxD
P1.1
SDO
RESET
SER/PAR
DIN
SCLK
SYNC
SPI/I2C
DVDD
Figure 37. AD5380-to-8051 Interface
AD5380 to ADSP-2101/ADSP-2103
Figure 38 shows a serial interface between the AD5380 and the
ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103 should
be set up to operate in SPORT transmit alternate framing mode.
The ADSP-2101/ADSP-2103 SPORT is programmed through
the SPORT control register and should be configured as follows:
internal clock operation, active low framing, and 16-bit word
length. Transmission is initiated by writing a word to the
Tx register after the SPORT has been enabled.
03731-038
ADSP-2101/
ADSP-2103
AD5380
DR
DT
SCK
TFS
RFS
SDO
RESET
SER/PAR
DIN
SCLK
DVDD
SPI/I2C
SYNC
Figure 38. AD5380-to-ADSP-2101/ADSP-2103 Interface
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