參數(shù)資料
型號(hào)： EVAL-AD5380EBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 24/40頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD5380
產(chǎn)品培訓(xùn)模塊： DAC Architectures
標(biāo)準(zhǔn)包裝： 1
DAC 的數(shù)量： 40
位數(shù)： 14
采樣率（每秒）： 125k
數(shù)據(jù)接口： DSP，I²C，MICROWIRE?，并行，QSPI?，SPI?
設(shè)置時(shí)間： 8µs
DAC 型： 電壓
工作溫度： -40°C ~ 85°C
已供物品： 板，CD
已用 IC / 零件： AD5380
AD5380
Data Sheet
Rev. C | Page 30 of 40
2-Byte Mode
Following initialization of 2-byte mode, the user can update
channels sequentially. The device address byte is only required
once and the pointer address pointer is configured for auto-
increment or burst mode.
The user must begin with an address byte (R/W = 0), after
which the DAC will acknowledge that it is prepared to receive
data by pulling SDA low. The address byte is followed by a
specific pointer byte (0xFF) that initiates the burst mode of
operation. The address pointer initializes to Channel 0, the
data following the pointer is loaded to Channel 0, and the
address pointer automatically increments to the next address.
The REG0 and REG1 bits in the data byte determine which
register will be updated. In this mode, following the initializa-
tion, only the two data bytes are required to update a channel.
The channel address automatically increments from Address 0
to Channel 39 and then returns to the normal 3-byte mode of
operation. This mode allows transmission of data to all
channels in one block and reduces the software overhead in
configuring all channels. A STOP condition at any time exits
this mode. Toggle mode is not supported in 2-byte mode.
Figure 33 shows a typical configuration.
PARALLEL INTERFACE
The SER/PAR pin must be tied low to enable the parallel inter-
face and disable the serial interfaces. Figure 7 shows the timing
diagram for a parallel write. The parallel interface is controlled
by the following pins:
CS Pin
Active low device select pin.
WR Pin
On the rising edge of WR, with CS low, the addresses on Pin A5
to Pin A0 are latched; data present on the data bus is loaded
into the selected input registers.
REG0, REG1 Pins
The REG0 and REG1 pins determine the destination register of
the data being written to the AD5380. See Table 10.
Pins A5 to A0
Each of the 40 DAC channels can be individually addressed.
Pins DB13 to DB0
The AD5380 accepts a straight 14-bit parallel word on DB13 to
DB0, where DB13 is the MSB and DB0 is the LSB.
1
0
1
0
1
AD1
AD0
R/W
A7 = 1
A6 = 1
A5 = 1
A4 = 1
A3 = 1
A2 = 1
A1 = 1
A0 = 1
START COND
BY MASTER
ADDRESS BYTE
POINTER BYTE
MOST SIGNIFICANT DATA BYTE
CHANNEL 0 DATA
LEAST SIGNIFICANT DATA BYTE
ACK BY
CONVERTER
MSB
ACK BY
CONVERTER
ACK BY
AD538x
ACK BY
AD538x
MOST SIGNIFICANT DATA BYTE
CHANNEL 1 DATA
LEAST SIGNIFICANT DATA BYTE
ACK BY
CONVERTER
ACK BY
CONVERTER
MOST SIGNIFICANT DATA BYTE
CHANNEL N DATA FOLLOWED BY STOP
LEAST SIGNIFICANT DATA BYTE
ACK BY
CONVERTER
ACK BY
CONVERTER
STOP
COND
BY
MASTER
REG1
REG0
MSB
LSB
MSB
LSB
REG1
REG0
MSB
LSB
MSB
LSB
REG1
REG0
MSB
LSB
MSB
LSB
SCL
SDA
SCL
SDA
SCL
SDA
SCL
SDA
03731-
033
Figure 33. 2-Byte, 12C Write Operation
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