參數(shù)資料
型號(hào)： EPF6024ATC144-3N
廠商： Altera
文件頁(yè)數(shù)： 52/52頁(yè)
文件大?。?/td> 0K
描述： IC FLEX 6000 FPGA 24K 144-TQFP
產(chǎn)品培訓(xùn)模塊： Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝： 180
系列： FLEX 6000
LAB/CLB數(shù)： 196
邏輯元件/單元數(shù)： 1960
輸入/輸出數(shù)： 117
門數(shù)： 24000
電源電壓： 3 V ~ 3.6 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 144-LQFP
供應(yīng)商設(shè)備封裝： 144-TQFP（20x20）
Altera Corporation
9
FLEX 6000 Programmable Logic Device Family Data Sheet
Figure 4. Logic Element
The programmable flipflop in the LE can be configured for D, T, JK, or SR
operation. The clock and clear control signals on the flipflop can be driven
by global signals, general-purpose I/O pins, or any internal logic. For
combinatorial functions, the flipflop is bypassed and the output of the
LUT drives the outputs of the LE. The LE output can drive both the local
interconnect and the FastTrack Interconnect.
The FLEX 6000 architecture provides two types of dedicated high-speed
data paths that connect adjacent LEs without using local interconnect
paths: carry chains and cascade chains. A carry chain supports high-speed
arithmetic functions such as counters and adders, while a cascade chain
implements wide-input functions such as equivalent comparators with
minimum delay. Carry and cascade chains connect LEs 2 through 10 in an
LAB and all LABs in the same half of the row. Because extensive use of
carry and cascade chains can reduce routing flexibility, these chains
should be limited to speed-critical portions of a design.
Chip-Wide Reset
Carry-In
Clock
Select
Carry-Out
Look-Up
T
able
(LUT)
Clear/ Preset
Logic
Carry
Chain
Cascade
Chain
Cascade-In
Cascade-Out
LE-Out
Programmable
Register
PRN
CLRN
DQ
Register Bypass
data1
data2
data3
data4
labctrl1
labctrl2
labctrl3
labctrl4
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