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參數(shù)資料
| 型號： | EPF6024ATC144-3N |
| 廠商： | Altera |
| 文件頁數(shù)： | 16/52頁 |
| 文件大小： | 0K |
| 描述： | IC FLEX 6000 FPGA 24K 144-TQFP |
| 產(chǎn)品培訓模塊： | Three Reasons to Use FPGA's in Industrial Designs |
| 標準包裝： | 180 |
| 系列： | FLEX 6000 |
| LAB/CLB數(shù)： | 196 |
| 邏輯元件/單元數(shù)： | 1960 |
| 輸入/輸出數(shù)： | 117 |
| 門數(shù)： | 24000 |
| 電源電壓： | 3 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 144-LQFP |
| 供應商設備封裝： | 144-TQFP（20x20） |
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Altera Corporation
23
FLEX 6000 Programmable Logic Device Family Data Sheet
I/O Elements
An IOE contains a bidirectional I/O buffer and a tri-state buffer. IOEs can
be used as input, output, or bidirectional pins. An IOE receives its data
signals from the adjacent local interconnect, which can be driven by a row
or column interconnect (allowing any LE in the device to drive the IOE) or
by an adjacent LE (allowing fast clock-to-output delays). A FastFLEXTM
I/O pin is a row or column output pin that receives its data signals from
the adjacent local interconnect driven by an adjacent LE. The IOE receives
its output enable signal through the same path, allowing individual
output enables for every pin and permitting emulation of open-drain
buffers. The Altera Compiler uses programmable inversion to invert the
data or output enable signals automatically where appropriate. Open-
drain emulation is provided by driving the data input low and toggling
the OE of each IOE. This emulation is possible because there is one OE per
pin.
A chip-wide output enable feature allows the designer to disable all pins
of the device by asserting one pin (DEV_OE). This feature is useful during
board debugging or testing.
Figure 12 shows the IOE block diagram.
Figure 12. IOE Block Diagram
From LAB Local Interconnect
Slew-Rate
Control
From LAB Local Interconnect
To Row or Column Interconnect
Chip-Wide Output Enable
Delay
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