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參數資料
| 型號： | EP20K60EFC672-3 |
| 廠商： | ALTERA CORP |
| 元件分類： | PLD |
| 英文描述： | LOADABLE PLD, PBGA672 |
| 封裝： | 27 X 27 MM, 1 MM PITCH, FINE LINE, BGA-672 |
| 文件頁數： | 60/114頁 |
| 文件大?。?/td> | 4116K |
| 代理商： | EP20K60EFC672-3 |
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Altera Corporation
5
Preliminary Information
APEX 20K Programmable Logic Device Family Data Sheet
Notes to tables:
(1)
Contact Altera for up-to-date information on package availability.
(2)
I/O counts include dedicated input and clock pins.
(3)
APEX 20K device package types include thin quad flat pack (TQFP), plastic quad flat pack (PQFP), power quad flat
pack (RQFP), 1.27-mm pitch ball-grid array (BGA), 1.00-mm pitch FineLine BGA, and pin-grid array (PGA)
packages.
(4)
All FineLine BGA packages, except the 144-pin and 1,020-pin packages, are footprint-compatible via SameFrame
pin-out. Therefore, designers can design a board to support a variety of devices, providing a flexible migration path
across densities and pin counts. Device migration is fully supported by Altera development tools. See “SameFrame
Pin-Outs” on page 45 for more information.
(5)
This device uses a thermally enhanced package, which is taller than the regular package. Consult the Altera Device
Package Information Data Sheet
for detailed package size information.
General
Description
APEX 20K devices are the first PLDs designed with the MultiCore
architecture, which combines the strengths of LUT-based and product-
term-based devices with an enhanced memory structure. LUT-based logic
provides optimized performance and efficiency for data-path, register-
intensive, mathematical, or digital signal processing (DSP) designs.
Product-term-based logic is optimized for complex combinatorial paths,
such as complex state machines. LUT- and product-term-based logic
combined with memory functions and a wide variety of MegaCore and
AMPP functions make the APEX 20K architecture uniquely suited for
system-on-a-programmable-chip designs. Applications historically
requiring a combination of LUT-, product-term-, and memory-based
devices can now be integrated into one APEX 20K device.
Table 5. APEX 20K QFP, BGA & PGA Package Sizes
Feature
144-Pin TQFP 208-Pin QFP 240-Pin QFP 356-Pin BGA 652-Pin BGA 655-Pin PGA
Pitch (mm)
0.50
1.27
–
Area (mm2)
484
924
1,218
1,225
2,025
3,906
Length
× Width
(mm
× mm)
22
× 22
30.4
× 30.4
34.9
× 34.9
35
× 35
45
× 45
62.5
× 62.5
Table 6. APEX 20K FineLine BGA Package Sizes
Feature
144 Pin
324 Pin
484 Pin
672 Pin
1,020 Pin
Pitch (mm)
1.00
Area (mm2)
169
361
529
729
1,089
Length
× Width (mm × mm)
13
× 13
19
× 19
23
× 23
27
× 27
33
× 33
相關PDF資料 |
PDF描述 |
|---|---|
| EP20K60EFC672 | LOADABLE PLD, PBGA672 |
| EP20K60EQC208 | LOADABLE PLD, PQFP208 |
| EP20K60EQC240 | LOADABLE PLD, PQFP240 |
| EP20K60ERC208 | LOADABLE PLD, PQFP208 |
| EP20K60ERC240 | LOADABLE PLD, PQFP240 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| EP20K60EFI144-1ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
| EP20K60EFI144-2ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
| EP20K60EFI144-3ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
| EP20K60EFI324-1ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
| EP20K60EFI324-2ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
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