參數(shù)資料
型號: EP20K60EFC672-3
廠商: ALTERA CORP
元件分類: PLD
英文描述: LOADABLE PLD, PBGA672
封裝: 27 X 27 MM, 1 MM PITCH, FINE LINE, BGA-672
文件頁數(shù): 54/114頁
文件大?。?/td> 4116K
代理商: EP20K60EFC672-3
IGLOO nano DC and Switching Characteristics
2- 30
Advance v0.2
Timing Characteristics
Applies to 1.5 V DC Core Voltage
Table 2-42 2.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Drive Strength
Speed Grade
tDOUT
tDP
tDIN
tPY
tPYS
tEOUT
tZL
tZH
tLZ
tHZ
Units
2 mA
STD
0.97
4.44
0.19
1.06
1.22
0.66
3.87
3.47
1.80
1.70
ns
4 mA
STD
0.97
4.44
0.19
1.06
1.22
0.66
3.87
3.47
1.80
1.70
ns
8 mA
STD
0.97
3.61
0.19
1.06
1.22
0.66
3.27
3.11
2.05
2.17
ns
8 mA
STD
0.97
3.61
0.19
1.06
1.22
0.66
3.27
3.11
2.05
2.17
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
Table 2-43 2.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Drive Strength
Speed Grade
tDOUT
tDP
tDIN
tPY
tPYS
tEOUT
tZL
tZH
tLZ
tHZ
Units
2 mA
STD
0.97
2.41
0.19
1.06
1.22
0.66
1.93
1.57
1.79
1.77
ns
4 mA
STD
0.97
2.41
0.19
1.06
1.22
0.66
1.93
1.57
1.79
1.77
ns
6 mA
STD
0.97
1.99
0.19
1.06
1.22
0.66
1.76
1.42
2.04
2.25
ns
8 mA
STD
0.97
1.99
0.19
1.06
1.22
0.66
1.76
1.42
2.04
2.25
ns
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
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