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參數(shù)資料
| 型號： | EP20K100ERI208-2ES |
| 元件分類： | 數(shù)字電位計 |
| 英文描述： | Single Digitally Controlled Potentiometer (XDCP™); Temperature Range: -40°C to 85°C; Package: 8-MSOP |
| 中文描述： | FPGA的 |
| 文件頁數(shù)： | 28/114頁 |
| 文件大?。?/td> | 1623K |
| 代理商： | EP20K100ERI208-2ES |
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Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
The counter mode uses two three-input LUTs: one generates the counter
data, and the other generates the fast carry bit. A 2-to-1 multiplexer
provides synchronous loading, and another AND gate provides
synchronous clearing. If the cascade function is used by an LE in counter
mode, the synchronous clear or load overrides any signal carried on the
cascade chain. The synchronous clear overrides the synchronous load.
LEs in arithmetic mode can drive out registered and unregistered versions
of the LUT output.
Clear & Preset Logic Control
Logic for the register’s clear and preset signals is controlled by LAB-wide
signals. The LE directly supports an asynchronous clear function. The
Quartus II software Compiler can use a NOT-gate push-back technique to
emulate an asynchronous preset. Moreover, the Quartus II software
Compiler can use a programmable NOT-gate push-back technique to
emulate simultaneous preset and clear or asynchronous load. However,
this technique uses three additional LEs per register. All emulation is
performed automatically when the design is compiled. Registers that
emulate simultaneous preset and load will enter an unknown state upon
power-up or when the chip-wide reset is asserted.
In addition to the two clear and preset modes, APEX 20K devices provide
a chip-wide reset pin (DEV_CLRn) that resets all registers in the device.
Use of this pin is controlled through an option in the Quartus II software
that is set before compilation. The chip-wide reset overrides all other
control signals. Registers using an asynchronous preset are preset when
the chip-wide reset is asserted; this effect results from the inversion
technique used to implement the asynchronous preset.
FastTrack Interconnect
In the APEX 20K architecture, connections between LEs, ESBs, and I/O
pins are provided by the FastTrack Interconnect. The FastTrack
Interconnect is a series of continuous horizontal and vertical routing
channels that traverse the device. This global routing structure provides
predictable performance, even in complex designs. In contrast, the
segmented routing in FPGAs requires switch matrices to connect a
variable number of routing paths, increasing the delays between logic
resources and reducing performance.
The FastTrack Interconnect consists of row and column interconnect
channels that span the entire device. The row interconnect routes signals
throughout a row of MegaLAB structures; the column interconnect routes
signals throughout a column of MegaLAB structures. When using the row
and column interconnect, an LE, IOE, or ESB can drive any other LE, IOE,
or ESB in a device. See Figure 9.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EP20K100ERI208-3ES | FPGA |
| EP20K100ERI240-1ES | FPGA |
| EP20K100ERI240-2ES | FPGA |
| EP20K100ERI240-3ES | FPGA |
| EP20K100ETC144-1ES | FPGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EP20K100ERI208-3ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
| EP20K100ERI240-1ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
| EP20K100ERI240-2ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
| EP20K100ERI240-3ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
| EP20K100ETC144-1 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 416 Macro 92 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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