參數(shù)資料
型號： EP20K1000EBC652-1ES
元件分類： 數(shù)字電位計
英文描述： Single Digitally Controlled Potentiometer (XDCP™), Low Noise/Low Power/I2C Bus/256 Taps; Temperature Range: -40°C to 85°C; Package: 8-MSOP
中文描述： FPGA的
文件頁數(shù)： 19/114頁
文件大?。?/td> 1623K
代理商： EP20K1000EBC652-1ES
12
Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
Each LAB contains dedicated logic for driving control signals to its LEs
and ESBs. The control signals include clock, clock enable, asynchronous
clear, asynchronous preset, asynchronous load, synchronous clear, and
synchronous load signals. A maximum of six control signals can be used
at a time. Although synchronous load and clear signals are generally used
when implementing counters, they can also be used with other functions.
Each LAB can use two clocks and two clock enable signals. Each LAB’s
clock and clock enable signals are linked (e.g., any LE in a particular LAB
using CLK1 will also use CLKENA1). LEs with the same clock but different
clock enable signals either use both clock signals in one LAB or are placed
into separate LABs.
If both the rising and falling edges of a clock are used in a LAB, both LAB-
wide clock signals are used.
The LAB-wide control signals can be generated from the LAB local
interconnect, global signals, and dedicated clock pins. The inherent low
skew of the FastTrack Interconnect enables it to be used for clock
distribution. Figure 4 shows the LAB control signal generation circuit.
Figure 4. LAB Control Signal Generation
Notes:
(1)
APEX 20KE devices have four dedicated clocks.
(2)
The LABCLR1 and LABCLR2 signals also control asynchronous load and asynchronous preset for LEs within the
LAB.
(3)
The SYNCCLR signal can be generated by the local interconnect or global signals.
SYNCCLR
or LABCLK2
(3)
SYNCLOAD
or LABCLKENA2
LABCLK1
LABCLKENA1
LABCLR2
(2)
LABCLR1
(2)
Dedicated
Clocks
Global
Signals
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
2 or 4
(1)
4
相關PDF資料
PDF描述
EP20K1000EBC652-2ES Single Digitally Controlled Potentiometer (XDCP™), Low Noise/Low Power/I2C Bus/256 Taps; Temperature Range: -40°C to 85°C; Package: 8-MSOP T&R
EP20K1000EBC652-3ES FPGA
EP20K1000EBI652-1ES Quad Digitally Controlled Potentiometers (XDCP™); Temperature Range: -40°C to 85°C; Package: 20-TSSOP
EP20K1000EBI652-2ES Quad Digitally Controlled Potentiometers (XDCP™); Temperature Range: -25°C to 85°C; Package: 20-TSSOP
EP20K1000EBI652-3ES Quad Digitally Controlled Potentiometers (XDCP™); Temperature Range: -40°C to 85°C; Package: 20-TSSOP
相關代理商/技術參數(shù)
參數(shù)描述
EP20K1000EBC652-1X 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 2560 Macros 488 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K1000EBC652-2 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 2560 Macros 488 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K1000EBC652-2ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K1000EBC652-2X 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 2560 Macros 488 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K1000EBC652-3 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 2560 Macro 488 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*