參數(shù)資料
型號: EFM32TG210F32
廠商: Energy Micro
文件頁數(shù): 84/136頁
文件大?。?/td> 0K
描述: MCU 32BIT 32KB FLASH 32-QFN
特色產(chǎn)品: EFM32 Tiny Gecko
標(biāo)準(zhǔn)包裝: 1
系列: Tiny Gecko
核心處理器: ARM? Cortex?-M3
芯體尺寸: 32-位
速度: 32MHz
連通性: EBI/EMI,I²C,IrDA,智能卡,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,DMA,POR,PWM,WDT
輸入/輸出數(shù): 24
程序存儲器容量: 32KB(32K x 8)
程序存儲器類型: 閃存
RAM 容量: 4K x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 3.8 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x12b,D/A 1x12b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 32-VQFN 裸露焊盤
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: 914-1034-6
...the world's most energy friendly microcontrollers
2011-02-04 - d0002_Rev1.00
51
www.energymicro.com
3.4.5 LDR, PC#relative
Load register from memory.
3.4.5.1 Syntax
LDR{type}{cond} Rt, label
LDRD{cond} Rt, Rt2, label
; Load two words
where:
type
is one of:
B
unsigned byte, zero extend to 32 bits.
SB
signed byte, sign extend to 32 bits.
H
unsigned halfword, zero extend to 32 bits.
SH
signed halfword, sign extend to 32 bits.
#
omit, for word.
cond
is an optional condition code, see Section 3.3.7 (p. 43) .
Rt
is the register to load or store.
Rt2
is the second register to load or store.
label
is a PC#relative expression. See Section 3.3.6 (p. 42) .
3.4.5.2 Operation
LDR
loads a register with a value from a PC-relative memory address. The memory address is specified
by a label or by an offset from the PC.
The value to load or store can be a byte, halfword, or word. For load instructions, bytes and halfwords
can either be signed or unsigned. See Section 3.3.5 (p. 42) .
label
must be within a limited range of the current instruction. Table 3.7 (p. 51) shows the possible
offsets between label and the PC.
Table 3.7. Offset ranges
Instruction type
Offset range
Word, halfword, signed halfword, byte, signed byte
#4095 to 4095
Two words
#1020 to 1020
Note
You might have to use the .W suffix to get the maximum offset range. See Section 3.3.8 (p.
3.4.5.3 Restrictions
In these instructions:
Rt can be SP or PC only for word loads
Rt2 must not be SP and must not be PC
Rt must be different from Rt2.
When Rt is PC in a word load instruction:
bit[0] of the loaded value must be 1 for correct execution, and a branch occurs to this halfword-aligned
address
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