參數(shù)資料
型號(hào): EFM32TG210F32
廠商: Energy Micro
文件頁(yè)數(shù): 31/136頁(yè)
文件大小: 0K
描述: MCU 32BIT 32KB FLASH 32-QFN
特色產(chǎn)品: EFM32 Tiny Gecko
標(biāo)準(zhǔn)包裝: 1
系列: Tiny Gecko
核心處理器: ARM? Cortex?-M3
芯體尺寸: 32-位
速度: 32MHz
連通性: EBI/EMI,I²C,IrDA,智能卡,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,DMA,POR,PWM,WDT
輸入/輸出數(shù): 24
程序存儲(chǔ)器容量: 32KB(32K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 4K x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 3.8 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x12b,D/A 1x12b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 32-VQFN 裸露焊盤
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: 914-1034-6
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)當(dāng)前第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)
...the world's most energy friendly microcontrollers
2011-02-04 - d0002_Rev1.00
126
www.energymicro.com
Implementation-specific
The behavior is not architecturally defined, and does not have to be
documented by individual implementations. Used when there are a number
of implementation options available and the option chosen does not affect
software compatibility.
Index register
In some load and store instruction descriptions, the value of this register
is used as an offset to be added to or subtracted from the base register
value to form the address that is sent to memory. Some addressing modes
optionally enable the index register value to be shifted prior to the addition
or subtraction.
See Also Base register.
Instruction cycle count
The number of cycles that an instruction occupies the Execute stage of the
pipeline.
Interrupt handler
A program that control of the processor is passed to when an interrupt occurs.
Interrupt vector
One of a number of fixed addresses in low memory, or in high memory if high
vectors are configured, that contains the first instruction of the corresponding
interrupt handler.
Little-endian (LE)
Byte ordering scheme in which bytes of increasing significance in a data word
are stored at increasing addresses in memory.
See Also Big-endian, Byte-invariant, Endianness.
Little-endian memory
Memory in which:
a byte or halfword at a word-aligned address is the least significant byte
or halfword within the word at that address
a byte at a halfword-aligned address is the least significant byte within the
halfword at that address.
See Also Big-endian memory.
Load/store architecture
A processor architecture where data-processing operations only operate on
register contents, not directly on memory contents.
Memory Protection Unit
(MPU)
Hardware that controls access permissions to blocks of memory. An MPU
does not perform any address translation.
Prefetching
In pipelined processors, the process of fetching instructions from memory to
fill up the pipeline before the preceding instructions have finished executing.
Prefetching an instruction does not mean that the instruction has to be
executed.
Read
Reads are defined as memory operations that have the semantics of a
load. Reads include the Thumb instructions LDM, LDR, LDRSH, LDRH, LDRSB,
LDRB
, and POP.
Region
A partition of memory space.
Reserved
A field in a control register or instruction format is reserved if the field is to
be defined by the implementation, or produces Unpredictable results if the
contents of the field are not zero. These fields are reserved for use in future
extensions of the architecture or are implementation#specific. All reserved
bits not used by the implementation must be written as 0 and read as 0.
Should Be One (SBO)
Write as 1, or all 1s for bit fields, by software. Writing as 0 produces
Unpredictable results.
相關(guān)PDF資料
PDF描述
MPC565CZP56 IC MPU 32BIT IM FLASH 388-PBGA
C8051F587-IQ IC 8051 MCU 96K FLASH 32-QFP
MC68HC11F1CFN2 IC MCU 512 EEPROM 2MHZ 68-PLCC
MC68HC11F1CFN3 IC MCU 512 EEPROM 3MHZ 68-PLCC
MC68HC11F1CFN4 IC MCU 512 EEPROM 4MHZ 68-PLCC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EFM32TG210F32-QFN32 制造商:Energy Micro AS 功能描述:TINY GECKO MCU - Tape and Reel 制造商:Energy Micro AS 功能描述:TINY GECKO MCU - Cut TR (SOS) 制造商:Energy Micro AS 功能描述:IC MCU 32BIT 32KB FLASH 32QFN
EFM32TG210F32-QFN32T 制造商:Energy Micro AS 功能描述:32 BIT ARM MPU, TINY GECKO - Trays
EFM32TG210F32-QFN32-T 制造商:Energy Micro AS 功能描述:IC MCU 32BIT 32KB FLASH 32QFN
EFM32-TG210F32-SK 功能描述:IC MICRO KIT GECKO 32QFN RoHS:是 類別:套件 >> 半導(dǎo)體產(chǎn)品 - IC 元件分類 系列:Tiny Gecko 其它有關(guān)文件:NXPLOGIC2-KIT-ND Contents 標(biāo)準(zhǔn)包裝:1 系列:74AUP 套件類型:邏輯 值:180 件 - 18 種值各 10 件 包裝:- 安裝類型:表面貼裝 包括封裝:6-XSON,8-XSON,8-XQFN 產(chǎn)品目錄頁(yè)面:2653 (CN2011-ZH PDF) 工具箱內(nèi)容:(10) 568-4391-1-ND - IC GATE MULT-FUNC CONFIG 6-XSON(10) 568-4390-1-ND - IC CONFIG MULT-FUNC GATE 6-XSON(10) 568-4389-1-ND - IC GATE DUAL FUNCTION 8-XSON(10) 568-4388-1-ND - IC GATE DUAL FUNCTION 8-XQFN(10) 568-4387-1-ND - IC F-F D-TYPE POS EDGE 8-XSON(10) 568-4386-1-ND - IC F-F D-TYPE POS EDGE 8-XQFN(10) 568-4385-1-ND - IC CONFIG MULTI-FUNC GATE 6-XSON(10) 568-4384-1-ND - IC EX-OR GATE 3-IN 6-XSON(10) 568-4383-1-ND - IC F-F D-TYPE POS EDGE 6-XSON(10) 568-4382-1-ND - IC LATCH D-TYPE 6-XSON更多... 其它名稱:NXPLOGIC2-KIT
EFM32TG210F32-T 制造商:Energy Micro AS 功能描述:IC MCU 32BIT 32KB FLASH 32QFN