參數(shù)資料
型號(hào): EFM32TG210F32
廠商: Energy Micro
文件頁(yè)數(shù): 17/136頁(yè)
文件大?。?/td> 0K
描述: MCU 32BIT 32KB FLASH 32-QFN
特色產(chǎn)品: EFM32 Tiny Gecko
標(biāo)準(zhǔn)包裝: 1
系列: Tiny Gecko
核心處理器: ARM? Cortex?-M3
芯體尺寸: 32-位
速度: 32MHz
連通性: EBI/EMI,I²C,IrDA,智能卡,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,DMA,POR,PWM,WDT
輸入/輸出數(shù): 24
程序存儲(chǔ)器容量: 32KB(32K x 8)
程序存儲(chǔ)器類(lèi)型: 閃存
RAM 容量: 4K x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 3.8 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x12b,D/A 1x12b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 32-VQFN 裸露焊盤(pán)
包裝: 標(biāo)準(zhǔn)包裝
其它名稱(chēng): 914-1034-6
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...the world's most energy friendly microcontrollers
2011-02-04 - d0002_Rev1.00
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4.4.4 SysTick Calibration Value Register
The CALIB register indicates the SysTick calibration properties and is a read only register. See the
register summary in Table 4.32 (p. 111) for its attributes. The bit assignments are:
31
0
TENMS
Reserved
23
24
30
SKEW
NOREF
29
Table 4.36. CALIB register bit assignments
Bits
Name
Function
[31]
NOREF
Reads as zero. Indicates that a the RTC counter bit 0 is provided as a reference clock.
[30]
SKEW
Reads as one. Calibration value for the 10ms inexact timing is not known because TENMS is not
known . This can affect the suitability of SysTick as a software real time clock.
[29:24]
-
Reserved.
[23:0]
TENMS
Read as 0x0036B0, which gives 10 ms ticks when running off a 14 MHz clock.
If calibration information is not known, calculate the calibration value required from the frequency of the
processor clock or external clock.
4.4.5 SysTick design hints and tips
The SysTick counter runs on the processor clock or bit 0 of the RTC counter value. If the clock signal in
use is stopped (e.g. in lower Energy Modes), the SysTick counter stops.
Ensure software uses aligned word accesses to access the SysTick registers.
4.5 Memory protection unit
This section describes the Memory protection unit (MPU).
The MPU divides the memory map into a number of regions, and defines the location, size, access
permissions, and memory attributes of each region. It supports:
independent attribute settings for each region
overlapping regions
export of memory attributes to the system.
The memory attributes affect the behavior of memory accesses to the region. The Cortex-M3 MPU
defines:
eight separate memory regions, 0-7
a background region.
When memory regions overlap, a memory access is affected by the attributes of the region with the
highest number. For example, the attributes for region 7 take precedence over the attributes of any
region that overlaps region 7.
The background region has the same memory access attributes as the default memory map, but is
accessible from privileged software only.
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