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| 型號(hào)： | EDD5104ADTA-6BL-E |
| 廠商： | ELPIDA MEMORY INC |
| 元件分類： | DRAM |
| 英文描述： | 512M bits DDR SDRAM |
| 中文描述： | 128M X 4 DDR DRAM, 0.7 ns, PDSO66 |
| 封裝： | LEAD FREE, PLASTIC, TSOP2-66 |
| 文件頁(yè)數(shù)： | 15/49頁(yè) |
| 文件大?。?/td> | 568K |
| 代理商： | EDD5104ADTA-6BL-E |
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EDD5104ADTA-E, EDD5108ADTA-E, EDD5116ADTA-E
Preliminary Data Sheet E0501E10 (Ver. 1.0)
15
Function Truth Table
The following tables show the operations that are performed when each command is issued in each state of the
DDR SDRAM.
Current state
/CS
/RAS /CAS /WE
Address
Command
Operation
Next state
Precharging*
1
H
×
×
×
×
DESL
NOP
ldle
L
H
H
H
×
NOP
NOP
ldle
L
H
H
L
×
BST
ILLEGAL*
11
—
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL*
11
—
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL*
11
—
L
L
H
H
BA, RA
ACT
ILLEGAL*
11
—
L
L
H
L
BA, A10
PRE, PALL
NOP
ldle
L
L
L
×
×
ILLEGAL
—
Idle*
2
H
×
×
×
×
DESL
NOP
ldle
L
H
H
H
×
NOP
NOP
ldle
L
H
H
L
×
BST
ILLEGAL*
11
—
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL*
11
—
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL*
11
—
L
L
H
H
BA, RA
ACT
Activating
Active
L
L
H
L
BA, A10
PRE, PALL
NOP
ldle
L
L
L
H
×
REF, SELF
Refresh/
Self refresh*
12
Mode register set*
12
ldle/
Self refresh
L
L
L
L
MODE
MRS
ldle
Refresh
(auto-refresh)*
3
H
×
×
×
×
DESL
NOP
ldle
L
H
H
H
×
NOP
NOP
ldle
L
H
H
L
×
BST
ILLEGAL
—
L
H
L
×
×
ILLEGAL
—
L
L
×
×
×
ILLEGAL
—
Activating*
4
H
×
×
×
×
DESL
NOP
Active
L
H
H
H
×
NOP
NOP
Active
L
H
H
L
×
BST
ILLEGAL*
11
—
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL*
11
—
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL*
11
—
L
L
H
H
BA, RA
ACT
ILLEGAL*
11
—
L
L
H
L
BA, A10
PRE, PALL
ILLEGAL*
11
—
L
L
L
×
×
ILLEGAL
—
Active*
5
H
×
×
×
×
DESL
NOP
Active
L
H
H
H
×
NOP
NOP
Active
L
H
H
L
×
BST
ILLEGAL
Active
L
H
L
H
BA, CA, A10
READ/READA
Starting read operation Read/READA
L
H
L
L
BA, CA, A10
WRIT/WRITA
Starting write operation
Write
recovering/
precharging
L
L
H
H
BA, RA
ACT
ILLEGAL*
11
—
L
L
H
L
BA, A10
PRE, PALL
Pre-charge
Idle
L
L
L
×
×
ILLEGAL
—
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EDD5104ADTA-7BL-E | AML22 Series, Electronic Control Pushbutton, Square, Standard Bezel, Lighted, 1 LED, DPDT, Momentary Action, Snap in panel mount |
| EDD5104ADTA-7A | 512M bits DDR SDRAM |
| EDD5104ADTA-7A-E | 512M bits DDR SDRAM |
| EDD5104ADTA-7AL | 512M bits DDR SDRAM |
| EDD5104ADTA-7B | 512M bits DDR SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EDD5104ADTA-7A | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR SDRAM |
| EDD5104ADTA-7A-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR SDRAM |
| EDD5104ADTA-7AL | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR SDRAM |
| EDD5104ADTA-7AL-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR SDRAM |
| EDD5104ADTA-7B | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR SDRAM |
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