參數(shù)資料
型號(hào)： EDD5104ADTA-7BL-E
廠商： ELPIDA MEMORY INC
元件分類： DRAM
英文描述： AML22 Series, Electronic Control Pushbutton, Square, Standard Bezel, Lighted, 1 LED, DPDT, Momentary Action, Snap in panel mount
中文描述： 128M X 4 DDR DRAM, 0.75 ns, PDSO66
封裝： LEAD FREE, PLASTIC, TSOP2-66
文件頁(yè)數(shù)： 1/49頁(yè)
文件大?。?/td> 568K
代理商： EDD5104ADTA-7BL-E
Document No. E0501E10 (Ver. 1.0)
Date Published March 2004 (K) Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2004
PRELIMINARY DATA SHEET
512M bits DDR SDRAM
EDD5104ADTA-E (128M words
×
4 bits)
EDD5108ADTA-E (64M words
×
8 bits)
EDD5116ADTA-E (32M words
×
16 bits)
Description
The
EDD5116AD are 512M bits Double Data Rate (DDR)
SDRAM. Read and write operations are performed at
the cross points of the CK and the /CK. This high-
speed data transfer is realized by the 2 bits prefetch-
pipelined architecture. Data strobe (DQS) both for
read and write are available for high speed and reliable
data bus design. By setting extended mode register,
the on-chip Delay Locked Loop (DLL) can be set
enable or disable. It is packaged in standard 66-pin
plastic TSOP (II).
EDD5104AD,
the
EDD5108AD
and
the
Features
Power supply: VDD, VDDQ = 2.5V
±
0.2V
Data Rate: 333Mbps/266Mbps (max.)
Double Data Rate architecture; two data transfers per
clock cycle
Bi-directional, data strobe (DQS) is transmitted
/received with data, to be used in capturing data at
the receiver
Data inputs, outputs, and DM are synchronized with
DQS
4 internal banks for concurrent operation
DQS is edge aligned with data for READs; center
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
Data mask (DM) for write data
Auto precharge option for each burst access
SSTL_2 compatible I/O
Programmable burst length (BL): 2, 4, 8
Programmable /CAS latency (CL): 2, 2.5
Programmable output driver strength: normal/weak
Refresh cycles: 8192 refresh cycles/64ms
7.8
μ
s maximum average periodic refresh interval
2 variations of refresh
Auto refresh
Self refresh
TSOP (II) package
with
lead free solder (Sn-Bi)
Pin Configurations
/xxx indicates active low signal.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
VSS
NC
VSSQ
NC
DQ3
VDDQ
NC
NC
VSSQ
NC
DQ2
VDDQ
NC
NC
VSSQ
DQS
NC
VREF
VSS
DM
/CK
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
66-pin Plastic TSOP(II)
(Top view)
VDD
DQ0
VDDQ
NC
DQ1
VSSQ
NC
DQ2
VDDQ
NC
DQ3
VSSQ
NC
NC
VDDQ
NC
NC
VDD
NC
NC
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
A10(AP)
A0
A1
A2
A3
VDD
VSS
DQ7
VSSQ
NC
DQ6
VDDQ
NC
DQ5
VSSQ
NC
DQ4
VDDQ
NC
NC
VSSQ
DQS
NC
VREF
VSS
DM
/CK
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
X 16
X 8
X 4
Address input
Bank select address
Data-input/output
Input and output data strobe
Chip select
Row address strobe command
Column address strobe command
Write enable
Input mask
Clock input
Differential clock input
Clock enable
Input reference voltage
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
A0 to A12
BA0, BA1
DQ0 to DQ15
DQS, LDQS, UDQS
/CS
/RAS
/CAS
/WE
DM, LDM, UDM
CK
/CK
CKE
VREF
VDD
VSS
VDDQ
VSSQ
NC
VDD
NC
VDDQ
NC
DQ0
VSSQ
NC
NC
VDDQ
NC
DQ1
VSSQ
NC
NC
VDDQ
NC
NC
VDD
NC
NC
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
A10(AP)
A0
A1
A2
A3
VDD
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSSQ
UDQS
NC
VREF
VSS
UDM
/CK
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDDQ
LDQS
NC
VDD
NC
LDM
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
A10(AP)
A0
A1
A2
A3
VDD
相關(guān)PDF資料
PDF描述
EDD5104ADTA-7A 512M bits DDR SDRAM
EDD5104ADTA-7A-E 512M bits DDR SDRAM
EDD5104ADTA-7AL 512M bits DDR SDRAM
EDD5104ADTA-7B 512M bits DDR SDRAM
EDD5104ADTA-7B-E 512M bits DDR SDRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EDD5104ADTA-E 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR SDRAM
EDD5108ABTA 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR SDRAM
EDD5108ABTA-6B 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR SDRAM
EDD5108ABTA-7A 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR SDRAM
EDD5108ABTA-7B 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR SDRAM
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