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參數(shù)資料
| 型號(hào)： | EDD5104ADTA-6BL-E |
| 廠商： | ELPIDA MEMORY INC |
| 元件分類： | DRAM |
| 英文描述： | 512M bits DDR SDRAM |
| 中文描述： | 128M X 4 DDR DRAM, 0.7 ns, PDSO66 |
| 封裝： | LEAD FREE, PLASTIC, TSOP2-66 |
| 文件頁數(shù)： | 13/49頁 |
| 文件大?。?/td> | 568K |
| 代理商： | EDD5104ADTA-6BL-E |
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EDD5104ADTA-E, EDD5108ADTA-E, EDD5116ADTA-E
Preliminary Data Sheet E0501E10 (Ver. 1.0)
13
Command Operation
Command Truth Table
DDR SDRAM recognize the following commands specified by the /CS, /RAS, /CAS, /WE and address pins. All other
combinations than those in the table below are illegal.
CKE
Command
Symbol
n – 1 n
/CS
/RAS /CAS /WE BA1 BA0 AP
Address
Ignore command
DESL
H
H
H
×
×
×
×
×
×
×
No operation
NOP
H
H
L
H
H
H
×
×
×
×
Burst stop in read command
BST
H
H
L
H
H
L
×
×
×
×
Column address and read command
READ
H
H
L
H
L
H
V
V
L
V
Read with auto-precharge
READA
H
H
L
H
L
H
V
V
H
V
Column address and write command
WRIT
H
H
L
H
L
L
V
V
L
V
Write with auto-precharge
WRITA
H
H
L
H
L
L
V
V
H
V
Row address strobe and bank active
ACT
H
H
L
L
H
H
V
V
V
V
Precharge select bank
PRE
H
H
L
L
H
L
V
V
L
×
Precharge all bank
PALL
H
H
L
L
H
L
×
×
H
×
Refresh
REF
H
H
L
L
L
H
×
×
×
×
SELF
H
L
L
L
L
H
×
×
×
×
Mode register set
MRS
H
H
L
L
L
L
L
L
L
V
Remark: H: VIH. L: VIL.
×
: VIH or VIL V: Valid address input
Note: The CKE level must be kept for 1 CK cycle at least.
Ignore command [DESL]
When /CS is High at the cross point of the CK rising edge and the VREF level, every input are neglected and internal
status is held.
No operation [NOP]
As long as this command is input at the cross point of the CK rising edge and the VREF level, address and data
input are neglected and internal status is held.
Burst stop in read operation [BST]
This command stops a burst read operation, which is not applicable for a burst write operation.
Column address strobe and read command [READ]
This command starts a read operation. The start address of the burst read is determined by the column address
(See “Address Pins Table” in Pin Function) and the bank select address. After the completion of the read operation,
the output buffer becomes High-Z.
Read with auto-precharge [READA]
This command starts a read operation. After completion of the read operation, precharge is automatically executed.
Column address strobe and write command [WRIT]
This command starts a write operation. The start address of the burst write is determined by the column address
(See “Address Pins Table” in Pin Function) and the bank select address.
Write with auto-precharge [WRITA]
This command starts a write operation. After completion of the write operation, precharge is automatically executed.
EMRS
H
H
L
L
L
L
L
H
L
V
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EDD5104ADTA-7BL-E | AML22 Series, Electronic Control Pushbutton, Square, Standard Bezel, Lighted, 1 LED, DPDT, Momentary Action, Snap in panel mount |
| EDD5104ADTA-7A | 512M bits DDR SDRAM |
| EDD5104ADTA-7A-E | 512M bits DDR SDRAM |
| EDD5104ADTA-7AL | 512M bits DDR SDRAM |
| EDD5104ADTA-7B | 512M bits DDR SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EDD5104ADTA-7A | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR SDRAM |
| EDD5104ADTA-7A-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR SDRAM |
| EDD5104ADTA-7AL | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR SDRAM |
| EDD5104ADTA-7AL-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR SDRAM |
| EDD5104ADTA-7B | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR SDRAM |
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