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參數(shù)資料
| 型號： | EBE41FE4ACFT-6E-E |
| 廠商： | ELPIDA MEMORY INC |
| 元件分類： | DRAM |
| 英文描述： | 512M X 72 DDR DRAM MODULE, DMA240 |
| 封裝： | ROHS COMPLIANT, FBDIMM-240 |
| 文件頁數(shù)： | 8/22頁 |
| 文件大?。?/td> | 205K |
| 代理商： | EBE41FE4ACFT-6E-E |
EBE41FE4ACFT
Data Sheet E1091E30 (Ver. 3.0)
16
Differential Receiver Input Specifications*
1
Parameter
Symbol
min.
max.
Unit
Comments
Differential peak-to-peak input
voltage
VRX-DIFFp-p
170
1300
mV
VRX-DIFFp-p = 2
×|VRX-D+ -VRX-D-|
Measured as note 2
Maximum single-ended voltage
for EI condition (AC + DC)
VRX-IDLE-SE
65
mV
3, 4, 5, 6
Maximum single-ended voltage
for EI condition (DC only)
VRX-IDLE-SE-DC
35
mV
3, 4, 5, 6, 7
Maximum peak-to-peak differential
voltage for EI condition
VRX-IDLE-DIFFp-p
65
mV
4, 5, 6
Single-ended voltage (w.r.t. VSS)
on D+/D-
VRX-SE
300
900
mV
5
Single-pulse peak differential input
voltage
VRX-DIFF-PULSE
85
mV
5, 8
Amplitude ratio between adjacent
symbols,
1100mV < VRX-DIFFp-p<= 1300mV
VRX-DIFF-ADJ
RATIO- HI
3.0
5, 9
Amplitude ratio between adjacent
symbols,
VRX-DIFFp-p <= 1100mV
VRX-DIFF-ADJ
RATIO
4.0
5, 9
Maximum RX inherent timing error TRX-TJ-MAX
0.4
UI
5, 10, 11
Maximum RX inherent
deterministic timing error
TRX-DJ-DD
0.3
UI
5, 10, 11, 12
Single-pulse width at zero-voltage
crossing
TRX-PW-ZC
0.55
UI
5, 8
Single-pulse width at minimum-
level crossing
TRX-PW-ML
0.2
UI
5, 8
Differential RX input rise/fall time
TRX-RISE,
TRX-FALL
50
ps
Given by 20%-80% voltage levels.
Common mode of the input voltage VRX-CM
120
400
mV
Defined as:
VRX-CM = DC (avg) of |VRX-D+
+ VRX-D-|/2
Measured as note 2.
See also note 13
AC peak-to-peak common mode of
input voltage
VRX-CM-ACp-p
270
mV
VRX-CM-AC =
Max |VRX-D+ + VRX-D-|/2 –
Min |VRX-D+ + VRX-D-|/2
Measured as note 2
Ratio of VRX-CM-ACp-p to
minimum VRX-DIFFp-p
VRX-CM-EH-Ratio
45
%
14
Differential return loss
RLRX-DIFF
9
dB
Measured over 0.1GHz to 2.4GHz.
See also note 15
Common mode return loss
RLRX-CM
6
dB
Measured over 0.1GHz to 2.4GHz.
See also note 15
RX termination resistance
RRX
41
55
16
D+/D- RX resistance difference
RRX-Match-DC
4
%
RRX-Match-DC =
2
×|RRX-D+ RRX-D-| / (RRX-D+
+ RRX-D-)
Lane-to-lane PCB skew at Rx
LRX-PCB-SKEW
6
UI
Lane-to-lane PCB skew at the
receiver that must be tolerated.
See also note 17
Minimum RX Drift Tolerance
TRX-DRIFT
400
ps
18
Minimum data tracking 3dB
bandwidth
FTRK
0.2
MHz
19
Electrical idle entry detect time
TEI-ENTRY -
DETECT
60
ns
20
Electrical idle exit detect time
TEI-EXIT -DETECT
30
ns
Bit Error Ratio
BER
10
-12
21
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