參數(shù)資料
型號: EBE41FE4ACFT-6E-E
廠商: ELPIDA MEMORY INC
元件分類: DRAM
英文描述: 512M X 72 DDR DRAM MODULE, DMA240
封裝: ROHS COMPLIANT, FBDIMM-240
文件頁數(shù): 2/22頁
文件大小: 205K
代理商: EBE41FE4ACFT-6E-E
EBE41FE4ACFT
Data Sheet E1091E30 (Ver. 3.0)
10
Electrical Specifications
All voltages are referenced to VSS (GND).
Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
Note
Voltage on any pin relative to VSS
VIN/VOUT
–0.3 to +1.75
V
AMB core power voltage relative to VSS
VCC
–0.3 to +1.75
V
DRAM interface power voltage relative to VSS
VDD
–0.5 to +2.30
V
Termination voltage relative to VSS
VTT
–0.5 to +2.30
V
Storage temperature
Tstg
–55 to +100
°C
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Operating Temperature Conditions
Parameter
Symbol
Value
Unit
Note
SDRAM component case temperature
TC
_DRAM
0 to
+95
°C
1
AMB component case temperature
TC
_AMB
110
°C
Note: 1. Supporting 0°C to +85°C and being able to extend to +95°C with doubling auto-refresh commands in
frequency to a 32ms period (tREFI = 3.9
s) and higher temperature self-refresh entry via the control of
EMRS (2) bit A7 is required.
DC Operating Conditions
Parameter
Symbol
min.
typ.
max.
Unit
Note
AMB supply voltage
VCC
1.455
1.50
1.575
V
DDR2 SDRAM supply voltage
VDD
1.7
1.8
1.9
V
Input termination voltage
VTT
0.48
× VDD
0.50
× VDD
0.52
× VDD
V
EEPROM supply voltage
VDDSPD
3.0
3.3
3.6
V
SPD input high voltage
VIH (DC)
2.1
VDDSPD
V
1
SPD input low voltage
VIL (DC)
0.8
V
1
RESET input high voltage
VIH (DC)
1.0
V
2
RESET input low voltage
VIL (DC)
0.5
V
2
Leakage current (RESET)
IL
–90
90
A
2
Leakage current (link)
IL
–5
5
A
3
Notes: 1. Applies for SMB and SPD bus signals.
2. Applies for AMB CMOS signal /RESET.
3. For all other AMB related DC parameters, please refer to the high-speed differential link interface
specification.
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