參數(shù)資料
型號(hào)： EBD11ED8ADFB-5
廠商： Elpida Memory, Inc.
英文描述： 1GB Unbuffered DDR SDRAM DIMM (128M words x72 bits, 2 Ranks)
中文描述： 1GB的無(wú)緩沖DDR SDRAM的內(nèi)存（128M的話(huà)x72位，2個(gè)等級(jí)）
文件頁(yè)數(shù)： 13/19頁(yè)
文件大?。?/td> 209K
代理商： EBD11ED8ADFB-5
EBD11ED8ABFB
Preliminary Data Sheet E0295E20 (Ver. 2.0)
13
-6B
-7A
-7B
Parameter
Symbol
min.
max.
min.
max
min.
max
Unit Notes
Auto refresh to Active/Auto
refresh command period
Active to Read/Write delay
tRFC
72
—
75
—
75
—
ns
tRCD
18
—
20
—
20
—
ns
Precharge to active
command period
Active to auto precharge
delay
Active to active command
period
tRP
18
—
20
—
20
—
ns
tRAP
tRCD min.
—
tRCD min.
—
tRCD min.
—
ns
tRRD
12
—
15
—
15
—
ns
Write recovery time
tWR
15
—
15
—
15
—
ns
Auto precharge write
Internal write to Read
command delay
Average periodic refresh
interval
Notes: 1. On all AC measurements, we assume the test conditions shown in the next page. For timing parameter
definitions, see ‘Timing Waveforms’ section.
2. This parameter defines the signal transition delay from the cross point of CK and /CK. The signal
transition is defined to occur when the signal level crossing VTT.
3. The timing reference level is VTT.
4. Output valid window is defined to be the period between two successive transition of data out or DQS
(read) signals. The signal transition is defined to occur when the signal level crossing VTT.
5. tHZ is defined as DOUT transition delay from Low-Z to High-Z at the end of read burst operation. The
timing reference is cross point of CK and /CK. This parameter is not referred to a specific DOUT voltage
level, but specify when the device output stops driving.
6. tLZ is defined as DOUT transition delay from High-Z to Low-Z at the beginning of read operation. This
parameter is not referred to a specific DOUT voltage level, but specify when the device output begins
driving.
7. Input valid windows is defined to be the period between two successive transition of data input or DQS
(write) signals. The signal transition is defined to occur when the signal level crossing VREF.
8. The timing reference level is VREF.
9. The transition from Low-Z to High-Z is defined to occur when the device output stops driving. A specific
reference voltage to judge this transition is not given.
10. tCK (max.) is determined by the lock range of the DLL. Beyond this lock range, the DLL operation is not
assured.
11. tCK = tCK (min.) when these parameters are measured. Otherwise, absolute minimum values of these
values are 10% of tCK.
12. VDD is assumed to be 2.5V ± 0.2V. VDD power supply variation per cycle expected to be less than
0.4V/400 cycle.
13. tDAL = (tWR/tCK)+(tRP/tCK)
For each of the terms above, if not already an integer, round to the next highest integer.
Example: For –7A Speed at CL = 2.5, tCK = 7.5ns, tWR = 15ns and tRP= 20ns,
tDAL = (15ns/7.5ns) + (20ns/7.5ns) = (2) + (3)
tDAL = 5 clocks
(tWR/tCK)+
(tRP/tCK)
—
(tWR/tCK)+
(tRP/tCK)
—
(tWR/tCK)+
(tRP/tCK)
—
tCK 13
tWTR
1
—
1
—
1
—
tCK
tREF
—
7.8
—
7.8
—
7.8
μs
相關(guān)PDF資料
PDF描述
EBD11ED8ADFB-5B Connector
EBD11ED8ADFB-5C 1GB Unbuffered DDR SDRAM DIMM (128M words x72 bits, 2 Ranks)
EBD11ED8ADFB-6B 1GB Unbuffered DDR SDRAM DIMM (128M words x72 bits, 2 Ranks)
EBD11ED8ADFB-7A 210390060
EBD11ED8ADFB-7B 1GB Unbuffered DDR SDRAM DIMM (128M words x72 bits, 2 Ranks)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EBD11ED8ADFB-5B 制造商:ELPIDA 制造商全稱(chēng):Elpida Memory 功能描述:1GB Unbuffered DDR SDRAM DIMM (128M words x72 bits, 2 Ranks)
EBD11ED8ADFB-5C 制造商:ELPIDA 制造商全稱(chēng):Elpida Memory 功能描述:1GB Unbuffered DDR SDRAM DIMM (128M words x72 bits, 2 Ranks)
EBD11ED8ADFB-6B 制造商:ELPIDA 制造商全稱(chēng):Elpida Memory 功能描述:1GB Unbuffered DDR SDRAM DIMM (128M words x72 bits, 2 Ranks)
EBD11ED8ADFB-7A 制造商:ELPIDA 制造商全稱(chēng):Elpida Memory 功能描述:1GB Unbuffered DDR SDRAM DIMM (128M words x72 bits, 2 Ranks)
EBD11ED8ADFB-7B 制造商:ELPIDA 制造商全稱(chēng):Elpida Memory 功能描述:1GB Unbuffered DDR SDRAM DIMM (128M words x72 bits, 2 Ranks)
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