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SAM4CP [DATASHEET]
43051E–ATPL–08/14
44
The Peripheral DMA Controller handles transfer requests from the channel according to the following priorities (Low to
High priorities):
11.3
APB/AHB Bridge
The SAM4CP embeds two peripheral bridges: one on each Matrix (Matrix 0 for CM4P0 and Matrix 1 for CM4P1).
The peripherals of the bridge corresponding to CM4P0 (APB0) are clocked by MCK, and the peripherals of the bridge
corresponding to CM4P1 (APB1) are clocked by CPBMCK.
11.4
Peripheral Signal Multiplexing on I/O Lines
The SAM4CP can multiplex the I/O lines of the peripheral set.
The SAM4CP PIO Controllers control up to 32 lines. Each line can be assigned to one of two peripheral functions: A or B.
The multiplexing tables in the paragraphs that follow define how the I/O lines of the peripherals A and B are multiplexed
on the PIO Controllers. The column “Comments” has been inserted in this table for the user’s own comments; it may be
used to track how pins are defined in an application.
Note that some peripheral functions which are output only, might be duplicated within the tables.
Table 11-2.
Peripheral DMA Controller (PDC0)
Instance name
Channel T/R
AES
Transmit
TWI0
Transmit
UART0
Transmit
USART1
Transmit
USART0
Transmit
USART2
Transmit
USART3
Transmit
USART4
Transmit
PPLC
Transmit
AES
Receive
TWI0
Receive
UART0
Receive
USART4
Receive
USART3
Receive
USART2
Receive
USART1
Receive
USART0
Receive
ADC
Receive
PPLC
Receive
Table 11-3.
Peripheral DMA Controller (PDC1)
Instance name
Channel T/R
UART1
Transmit
SPI1
Transmit
UART1
Receive
SPI1
Receive