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SAM4CP [DATASHEET]
43051E–ATPL–08/14
12.11.1 MPU Access Permission Attributes
This section describes the MPU access permission attributes. The access permission bits (TEX, C, B, S, AP, and XN) of
the MPU_RASR control the access to the corresponding memory region. If an access is made to an area of memory
without the required permissions, then the MPU generates a permission fault.
The table below shows the encodings for the TEX, C, B, and S access permission bits.
Notes: 1.
The MPU ignores the value of this bit.
Table 12-38
shows the cache policy for memory attribute encodings with a TEX value is in the range 4-7.
Table 12-37. TEX, C, B, and S Encoding
TEX
C
B
S
Memory Type
Shareability
Other Attributes
b000
0
0
x
(1)
Strongly-ordered
Shareable
-
1
x
(1)
Device
Shareable
-
1
0
0
Normal
Not shareable
Outer and inner write-through. No write
allocate.
1
Shareable
1
0
Normal
Not shareable
Outer and inner write-back. No write
allocate.
1
Shareable
b001
0
0
0
Normal
Not shareable
-
1
Shareable
1
x
(1)
Reserved encoding
-
1
0
x
(1)
Implementation defined attributes.
-
1
0
Normal
Not shareable
Outer and inner write-back. Write and read
allocate.
1
Shareable
b010
0
0
x
(1)
Device
Not shareable
Nonshared Device.
1
x
(1)
Reserved encoding
-
1
x
(1)
x
(1)
Reserved encoding
-
b1BB
A
A
0
Normal
Not shareable
-
1
Shareable
Table 12-38. Cache Policy for Memory Attribute Encoding
Encoding, AA or BB
Corresponding Cache Policy
00
Non-cacheable
01
Write back, write and read allocate
10
Write through, no write allocate
11
Write back, no write allocate