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參數(shù)資料
| 型號(hào)： | DS33R41+ |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 321/335頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX ETHERNET MAP 400-BGA |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 收發(fā)器 |
| 驅(qū)動(dòng)器/接收器數(shù)： | 4/4 |
| 規(guī)程： | T1/E1/J1 |
| 電源電壓： | 3.14 V ~ 3.47 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 400-BBGA |
| 供應(yīng)商設(shè)備封裝： | 400-PBGA（27x27） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁(yè)面： | 1429 (CN2011-ZH PDF) |
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DS33R41 Inverse-Multiplexing Ethernet Mapper with Quad Integrated T1/E1/J1 Transceivers
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10.11 Channel Blocking Registers
The receive channel blocking registers (TR.RCBR1/TR.RCBR2/TR.RCBR3/TR.RCBR4) and the transmit channel
blocking registers (TR.TCBR1/TR.TCBR2/TR.TCBR3/TR.TCBR4) control RCHBLK and TCHBLK pins,
respectively. The RCHBLK and TCHBLK pins are user-programmable outputs that can be forced either high or low
during individual channels. These outputs can be used to block clocks to a USART or LAPD controller in ISDN-PRI
applications. When the appropriate bits are set to a 1, the RCHBLK and TCHBLK pins are held high during the
entire corresponding channel time. Channels 25 through 32 are ignored when the device is operated in the T1
mode.
10.12 Elastic Stores Operation
The device contains dual two-frame elastic stores, one for the receive direction and one for the transmit direction.
Both elastic stores are fully independent. The transmit and receive-side elastic stores can be enabled/disabled
independently of each other. Also, each elastic store can interface to either a 1.544MHz or
2.048MHz/4.096MHz/8.192MHz/16.384MHz backplane without regard to the backplane rate the other elastic store
is interfacing to. In most DS33R41 applications, all elastic stores will be enabled.
The elastic stores have two main purposes. Firstly, they can be used for rate conversion. When the device is in the
T1 mode, the elastic stores can rate-convert the T1 data stream to a 2.048MHz backplane. In E1 mode, the elastic
store can rate-convert the E1 data stream to a 1.544MHz backplane. Secondly, they can be used to absorb the
differences in frequency and phase between the T1 or E1 data stream and an asynchronous (i.e., not locked)
backplane clock, which can be 1.544MHz or 2.048MHz. In this mode, the elastic stores manage the rate difference
and perform controlled slips, deleting or repeating frames of data in order to manage the difference between the
network and the backplane. The elastic stores can also be used to multiplex T1 or E1 data streams into higher
backplane rates.
The elastic stores are used to multiplex the four T1/E1 data streams into an 8.192MHz backplane rate for
connection with the integrated Ethernet Mapper. See the Interleaved PCM Bus Operation section.
10.12.1 Receive Side
See the TR.IOCR1 and TR.IOCR2 registers for information on clock and I/O configurations. If the receive-side
elastic store is enabled, then the user must provide either a 1.544MHz or 2.048MHz clock at the RSYSCLK pin.
For higher rate system-clock applications, see the Interleaved PCM Bus Operation section. The user has the
option of either providing a frame/multiframe sync at the RSYNC pin or having the RSYNC pin provide a pulse on
frame/multiframe boundaries. If signaling reinsertion is enabled, signaling data in TS16 is realigned to the
multiframe-sync input on RSYNC. Otherwise, a multiframe-sync input on RSYNC is treated as a simple frame
boundary by the elastic store. The framer will always indicate frame boundaries on the network side of the elastic
store via the RFSYNC output whether the elastic store is enabled or not. Multiframe boundaries will always be
indicated via the RMSYNC output. If the elastic store is enabled, then RMSYNC will output the multiframe
boundary on the backplane side of the elastic store.
10.12.1.1 T1 Mode
If the user selects to apply a 2.048MHz clock to the RSYSCLK pin, then the data output at RSERO will be forced to
all ones every fourth channel and the F-bit will be passed into the MSB of TS0. Hence, channels 1 (bits 1–7), 5, 9,
13, 17, 21, 25, and 29 (time slots 0 (bits 1–7), 4, 8, 12, 16, 20, 24, and 28) will be forced to a one. Also, in
2.048MHz applications, the RCHBLK output will be forced high during the same channels as the RSERO pin. This
is useful in T1 to E1 conversion applications. If the two-frame elastic buffer either fills or empties, a controlled slip
will occur. If the buffer empties, then a full frame of data will be repeated at RSERO and the TR.SR5.0 and
TR.SR5.1 bits will be set to a one. If the buffer fills, then a full frame of data will be deleted and the TR.SR5.0 and
TR.SR5.2 bits will be set to a one.
10.12.1.2 E1 Mode
If the elastic store is enabled, then either CAS or CRC-4 multiframe boundaries will be indicated via the RMSYNC
output. If the user selects to apply a 1.544MHz clock to the RSYSCLK pin, then every fourth channel of the
received E1 data will be deleted and a F-bit position (which will be forced to one) will be inserted. Hence, channels
1, 5, 9, 13, 17, 21, 25, and 29 (time slots 0, 4, 8, 12, 16, 20, 24, and 28) will be deleted from the received E1 data
stream. Also, in 1.544MHz applications, the RCHBLK output will not be active in channels 25 through 32 (or in
other words, RCBR4 is not active). If the two-frame elastic buffer either fills or empties, a controlled slip will occur.
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