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DS33R41 Inverse-Multiplexing Ethernet Mapper with Quad Integrated T1/E1/J1 Transceivers
127 of 335
ADDR
NAME
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
34
TR.E1RCR2
—
RCLA
35
TR.E1TCR1
TFPT
T16S
TUA1
TSiS
TSA1
THDB3
TG802
TCRC4
36
TR.E1TCR2
Reserved
AEBE
AAIS
ARA
37
TR.BOCC
—
RBOCE
RBR
RBF1
RBF0
SBOC
38
TR.RSINFO1
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
39
TR.RSINFO2
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
3A
TR.RSINFO3
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
3B
TR.RSINFO4
—
—-
CH30
CH29
CH28
CH27
CH26
CH25
3C
TR.RSCSE1
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
3D
TR.RSCSE2
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
3E
TR.RSCSE3
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
3F
TR.RSCSE4
—
CH30
CH29
CH28
CH27
CH26
CH25
40
TR.SIGCR
GRSRE
—
RFE
RFF
RCCS
TCCS
FRSAO
41
TR.ERCNT
—
MECU
ECUS
EAMS
VCRFS
FSBE
MOSCRF
LCVCRF
42
TR.LCVCR1
LCVC15
LCVC14
LCVC13
LCVC12
LCVC11
LCVC10
LCVC9
LCCV8
43
TR.LCVCR2
LCVC7
LCVC6
LCVC5
LCVC4
LCVC3
LCVC2
LCVC1
LCVC0
44
TR.PCVCR1
PCVC15
PCVC14
PCVC13
PCVC12
PCVC11
PCVC10
PCVC9
PCVC8
45
TR.PCVCR2
PCVC7
PCVC6
PCVC5
PCVC4
PCVC3
PCVC2
PCVC1
PCVC0
46
TR.FOSCR1
FOS15
FOS14
FOS13
FOS12
FOS11
FOS10
FOS9
FOS8
47
TR.FOSCR2
FOS7
FOS6
FOS5
FOS4
FOS3
FOS2
FOS1
FOS0
48
TR.EBCR1
EB15
EB14
EB13
EB12
EB11
EB10
EB9
EB8
49
TR.EBCR2
EB7
EB6
EB5
EB4
EB3
EB2
EB1
EB0
4A
TR.LBCR
LTS
—
Reserved
LLB
RLB
PLB
FLB
4B
TR.PCLR1
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
4C
TR.PCLR2
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
4D
TR.PCLR3
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
4E
TR.PCLR4
CH32
CH31
CH30
CH29
CH28
CH27
CH26
CH25
4F
TR.ESCR
TESALGN
TESR
TESMDM
TESE
RESALGN
RESR
RESMDM
RESE
50
TR.TS1
Transmit Signaling Bit Format Changes With Operating Mode. See Register Definition.
51
TR.TS2
Transmit Signaling Bit Format Changes With Operating Mode. See Register Definition.
52
TR.TS3
Transmit Signaling Bit Format Changes With Operating Mode. See Register Definition.
53
TR.TS4
Transmit Signaling Bit Format Changes With Operating Mode. See Register Definition.
54
TR.TS5
Transmit Signaling Bit Format Changes With Operating Mode. See Register Definition.
55
TR.TS6
Transmit Signaling Bit Format Changes With Operating Mode. See Register Definition.
56
TR.TS7
Transmit Signaling Bit Format Changes With Operating Mode. See Register Definition.
57
TR.TS8
Transmit Signaling Bit Format Changes With Operating Mode. See Register Definition.
58
TR.TS9
Transmit Signaling Bit Format Changes With Operating Mode. See Register Definition.
59
TR.TS10
Transmit Signaling Bit Format Changes With Operating Mode. See Register Definition.
5A
TR.TS11
Transmit Signaling Bit Format Changes With Operating Mode. See Register Definition.
5B
TR.TS12
Transmit Signaling Bit Format Changes With Operating Mode. See Register Definition.
5C
TR.TS13
Transmit Signaling Bit Format Changes With Operating Mode. See Register Definition.
5D
TR.TS14
Transmit Signaling Bit Format Changes With Operating Mode. See Register Definition.
5E
TR.TS15
Transmit Signaling Bit Format Changes With Operating Mode. See Register Definition.
5F
TR.TS16
Transmit Signaling Bit Format Changes With Operating Mode. See Register Definition.
60
TR.RS1
Receive Signaling Bit Format Changes With Operating Mode. See Register Definition.
61
TR.RS2
Receive Signaling Bit Format Changes With Operating Mode. See Register Definition.
62
TR.RS3
Receive Signaling Bit Format Changes With Operating Mode. See Register Definition.
63
TR.RS4
Receive Signaling Bit Format Changes With Operating Mode. See Register Definition.
64
TR.RS5
Receive Signaling Bit Format Changes With Operating Mode. See Register Definition.
65
TR.RS6
Receive Signaling Bit Format Changes With Operating Mode. See Register Definition.
66
TR.RS7
Receive Signaling Bit Format Changes With Operating Mode. See Register Definition.
67
TR.RS8
Receive Signaling Bit Format Changes With Operating Mode. See Register Definition.
68
TR.RS9
Receive Signaling Bit Format Changes With Operating Mode. See Register Definition.
69
TR.RS10
Receive Signaling Bit Format Changes With Operating Mode. See Register Definition.
6A
TR.RS11
Receive Signaling Bit Format Changes With Operating Mode. See Register Definition.
6B
TR.RS12
Receive Signaling Bit Format Changes With Operating Mode. See Register Definition.
6C
TR.RS13
Receive Signaling Bit Format Changes With Operating Mode. See Register Definition.