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| 型號(hào)： | DS32512N# |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 56/130頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU DS3/E3/STS-1 484-BGA |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 類型： | 線路接口裝置（LIU） |
| 規(guī)程： | DS3 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 484-BGA |
| 供應(yīng)商設(shè)備封裝： | 484-BGA（23x23） |
| 包裝： | 管件 |
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DS32506/DS32508/DS32512
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(AT&T 734A or equivalent). The AGC and the equalizer work simultaneously but independently to supply a signal
of nominal amplitude and pulse shape to the clock and data recovery block. The AGC/equalizer block automatically
handles direct (0 meters) monitoring of the transmitter output signal. The real-time receiver gain level can be read
from the LIU.RGLR register. Note: When the receiver preamp is on (LIU.SR:RPAS = 1), the actual receiver gain
level is the level read from the LIU.RGLR register plus 14dB.
8.3.4 Clock and Data Recovery (CDR)
The CDR block takes the amplified, equalized signal from the AGC/equalizer block and produces separate clock,
positive data, and negative data signals. The CDR operates from the LIU’s reference clock. See Section 8.7.1 for
more information about reference clocks and clock selection.
The receiver locks onto the incoming signal using a clock recovery PLL. The PLL lock status is indicated in the
LIU.SR:RLOL status bit. The RLOL bit is set when the difference between recovered clock frequency and reference
clock frequency is greater than 7900ppm and cleared when the difference is less than 7700ppm. A change of state
of the RLOL status bit can cause an interrupt if enabled by LIU.SRIE:RLOLIE. Note that if the reference clock is not
present, RLOL is not set.
8.3.5 Loss-of-Signal (LOS) Detector
The receiver contains analog and digital LOS detectors. The analog LOS (ALOS) detector resides in the
AGC/equalizer block. At approximately 23dB below nominal pulse amplitude ALOS is declared by setting the
LIU.SR:ALOS status bit. A change of state of the ALOS status bit can cause an interrupt if enabled by
LIU.SRIE:ALOSIE. When ALOS is declared the CDR block forces all zeros out of the data recovery circuit, causing
digital LOS (DLOS), which is indicated by the RLOS pin and the LINE.RSR:LOS status bit. During ALOS the RCLK
pin follows the LIU’s reference clock, since no clock information is being received on RXP/RXN. ALOS is cleared at
approximately 22dB below nominal pulse amplitude. When the preamp is enabled (Section 8.3.2) ALOS is declared
at approximately 37dB below nominal and cleared at approximately 36dB below nominal.
The digital LOS detector declares DLOS when it detects 192 consecutive zeros in the recovered data stream.
When DLOS occurs, the receiver asserts the RLOS pin (if the hardware interface is enabled) and the
LINE.RSR:LOS status bit. DLOS is cleared when there are no EXZ occurrences over a span of 192 clock periods.
An EXZ occurrence is defined as three or more consecutive zeros in DS3 and STS-1 modes and four or more
consecutive zeros in E3 mode. The RLOS pin and the LOS status bit are deasserted when the DLOS condition is
cleared. A change of state of the LINE.RSR:LOS status bit can cause an interrupt if enabled by
LINE.RSRIE:LOSIE. DLOS is only declared when B3ZS/HDB3 decoding is enabled (LINE.RCR:RZSD = 0). When
B3ZS/HDB3 decoding is disabled in the LIU, decoding should be enabled in the neighboring DS3/E3 framer, and
DLOS should be detected and report by the framer.
The requirements of ANSI T1.231 and ITU-T G.775 for DS3 LOS defects are met by the DLOS detector, which
asserts RLOS when it counts 192 consecutive zeros coming out of the CDR block and clears RLOS when it counts
192 consecutive pulse intervals without excessive zero occurrences.
The requirements of ITU-T G.775 for E3 LOS defects are met by a combination of the ALOS detector and the
DLOS detector, as follows:
For E3 RLOS Assertion:
1) The ALOS detector in the AGC/equalizer block detects that the incoming signal is less than or
equal to a signal level approximately 23dB below nominal, and mutes the data coming out of
the clock and data recovery block. (23dB below nominal is in the “tolerance range” of G.775,
where LOS may or may not be declared.)
2) The DLOS detector counts 192 consecutive zeros coming out of the CDR block and asserts
RLOS. (192 meets the 10
≤ N ≤ 255 pulse-interval duration requirement of G.775.)
For E3 RLOS Clear:
1) The ALOS detector in the AGC/equalizer block detects that the incoming signal is greater than
or equal to a signal level approximately 22dB below nominal, and enables data to come out of
the CDR block. (22dB is in the “tolerance range” of G.775, where LOS may or may not be
declared.)
2) The DLOS detector counts 192 consecutive pulse intervals without EXZ occurrences and
deasserts RLOS. (192 meets the 10
≤ N ≤ 255 pulse-interval duration requirement of G.775.)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS32512N# | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 12-Port DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS32512N+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 12-Port DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS32512NA2 | 制造商:Maxim Integrated Products 功能描述:DS32512 X12 DS3/E3 LIU REVA2 IND - Rail/Tube |
| DS32512NW | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS32512W | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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