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| 型號(hào)： | DS32512N# |
| 廠(chǎng)商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 49/130頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU DS3/E3/STS-1 484-BGA |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 類(lèi)型： | 線(xiàn)路接口裝置（LIU） |
| 規(guī)程： | DS3 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 484-BGA |
| 供應(yīng)商設(shè)備封裝： | 484-BGA（23x23） |
| 包裝： | 管件 |
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DS32506/DS32508/DS32512
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1s where the polarity of the first 1 is opposite the polarity of the BPV in the last B3ZS/HDB3 codeword. The first 1 is
transmitted according to the normal AMI rule, but the second 1 is transmitted with the same polarity as the first 1,
thus making the second 1 a bipolar violation.
If the transmitter is configured for binary interface format (Section 8.2.2.2) and EXZI = 1, then when the configured
manual error insert control goes from zero to one, the transmitter waits for the next occurrence of three (four)
consecutive zeros in the transmit data stream and inhibits the replacement of those zeros with a B3ZS (HDB3)
codeword.
The transmitter ensures that there is at least one intervening 1 between consecutive BPV or EXZ errors. If a
second error insertion request of a given type (BPV or EXZ) is initiated before a previous request has been
completed, the second request is ignored.
8.2.4 AIS Generation
The transmitter can be configured to transmit an AIS signal by asserting the TAIS pin or the PORT.CR3:TAIS
configuration bit. The type of AIS signal to be generated is specified by the LIU mode (LMn[1:0] pins or
PORT.CR2:LM[1:0] configuration bits) and the AIS type (AIST pin or PORT.CR3:AIST configuration bit). When
AIST = 0, the AIS signal is unframed all ones for DS3, E3 and STS-1 modes. When AIST = 1, the AIS signal is the
framed DS3 AIS signal in DS3 mode, unframed all ones in E3 mode, and the AIS-L signal in STS-1 mode. The
AIS-L signal is normally scrambled, but scrambling can be disabled by setting PORT.CR3:SCRD = 1.
8.2.5 Waveshaping
8.2.5.1
Standards-Compliant Waveshaping
Waveshaping converts the transmit clock, positive data, and negative data signals into a single analog AMI signal
with the waveshape required for interfacing to DS3/E3/STS-1 lines. Figure 8-1 and Table 8-2 show the DS3
waveform equations and template. Figure 8-2 and Table 8-4 show the STS-1 waveform equations and template.
Figure 8-3 shows the E3 waveform template.
8.2.5.2
Programmable Waveshaping
The transmit waveshape can be adjusted with the TWSC[19:0] bits in the LIU.TWSCR1 and LIU.TWSCR2
registers. These signals control the amplitude, slew rates and various other aspects of the waveform template. See
the register descriptions for further details.
8.2.6 Line Build-Out
Because DS3 and STS-1 signals must meet the waveform templates at the cross-connect through any cable length
from 0 to 450 feet, the waveshaping circuitry includes a selectable LBO feature. For cable lengths of 225 feet or
greater, both the TLBO pin and the LIU.CR1:TLBO configuration bit should be low to disable the LBO circuitry.
When the LBO circuitry is disabled, output pulses are driven onto the coaxial cable without any preattenuation. For
cable lengths less than 225 feet, either the TLBO pin or the LIU.CR1:TLBO configuration bit should be high to
enable the LBO circuitry. When the LBO circuitry is enabled, pulses are preattenuated by the LBO circuitry before
being driven onto the coaxial cable to provide attenuation that mimics the attenuation of 225 feet of coaxial cable.
8.2.7 Line Driver
The transmit line driver can be disabled (TXP and TXN outputs high impedance) by deasserting the TOE pin and
deasserting the LIU.CR1:TOE configuration bit. Powering down the transmitter through the TPD pin or the
PORT.CR1:TPD configuration bit also disables the transmit line driver.
8.2.8 Interfacing to the Line
The transmitter interfaces to the outgoing DS3/E3/STS-1 coaxial cable (75
Ω) through a 1:1 isolation transformer
connected to the TXP and TXN pins. The transmit line termination can be internal to the device, external to the
device, or a combination of both. Figure 4-1 shows the arrangement of the transformer when the internal
termination is enabled (LIU.CR1:TTRE = 1) and no external termination resistors are used. Figure 4-2 shows the
arrangement of the transformer and external termination resistors when the internal termination is disabled
(LIU.CR1:TTRE = 0). The internal termination resistor value for the transmitter is specified in LIU.CR1:TRESADJ.
Table 8-7 and Table 8-8 specify the required characteristics of the transformer and provide a list of recommended
transformers.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS32512N# | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 12-Port DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS32512N+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 12-Port DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS32512NA2 | 制造商:Maxim Integrated Products 功能描述:DS32512 X12 DS3/E3 LIU REVA2 IND - Rail/Tube |
| DS32512NW | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS32512W | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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