參數(shù)資料
型號: DS32506N+
廠商: Maxim Integrated Products
文件頁數(shù): 96/130頁
文件大?。?/td> 0K
描述: IC LIU DS3/E3/STS-1 484-BGA
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 60
類型: 線路接口裝置(LIU)
規(guī)程: IEEE 1149.1
電源電壓: 1.8V, 3.3V
安裝類型: 表面貼裝
封裝/外殼: 484-BGA
供應(yīng)商設(shè)備封裝: 484-BGA(23x23)
包裝: 管件
DS32506/DS32508/DS32512
68 of 130
Register Name:
PORT.SR
Register Description:
Port Status Register
Register Address:
n * 80h + 18h
Bit #
15
14
13
12
11
10
9
8
Name
Default
Bit #
7
6
5
4
3
2
1
0
Name
PMS
Default
0
Bit 0: Performance Monitoring Update Status (PMS).
This bit is set when the PMS bits are set in all of the port
functional blocks that are configured for port-level update control (i.e., all blocks that have PMUM = 1). Blocks that
have PMUM = 0 have no effect on this bit. In port-level software update mode, the port update request bit
(PORT.CR1:PMU) should be held high until this status bit goes high. See Section 8.7.4.
0 = The associated update request signal is low or not all register updates are completed.
1 = The requested performance register updates are all completed.
Register Name:
PORT.SRL
Register Description:
Port Status Register Latched
Register Address:
n * 80h + 1Ah
Bit #
15
14
13
12
11
10
9
8
Name
TCLKL
Bit #
7
6
5
4
3
2
1
0
Name
PMSL
Bit 8: Transmit Clock Activity Status Latched (TCLKL).
This bit is set when the signal on the TCLK pin used by
this port (TCLKn when TCC = 0, TCLK1 when TCC = 1) is active. When set, this bit causes an interrupt if interrupt
enables PORT.SRIE:TCLKIE, PORT.ISRIE:PSRIE, and GLOBAL.ISRIE: PnISRIE are all set.
Bit 0: Performance Monitoring Update Status Latched (PMSL).
This bit is set when the PORT.SR:PMS status
bit changes from low to high. When set, this bit causes an interrupt if interrupt enables PORT.SRIE:PMSIE,
PORT.ISRIE:PSRIE and GLOBAL.ISRIE:PnISRIE are all set. See Section 8.7.4.
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