參數(shù)資料
型號(hào): DS32506N+
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 90/130頁(yè)
文件大?。?/td> 0K
描述: IC LIU DS3/E3/STS-1 484-BGA
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 60
類型: 線路接口裝置(LIU)
規(guī)程: IEEE 1149.1
電源電壓: 1.8V, 3.3V
安裝類型: 表面貼裝
封裝/外殼: 484-BGA
供應(yīng)商設(shè)備封裝: 484-BGA(23x23)
包裝: 管件
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DS32506/DS32508/DS32512
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9.4 Port Common Registers
Table 9-4. Port Common Register Map
ADDRESS
OFFSET
REGISTER
REGISTER DESCRIPTION
00h
Port Control Register 1
02h
Port Control Register 2
04h
Port Control Register 3
06h
Unused
08h
Unused
0Ah
Port I/O Invert Control Register
0Ch
Unused
0Eh
Unused
10h
Port Interrupt Status Register
12h
Unused
14h
Port Interrupt Status Register Interrupt Enable
16h
Unused
18h
Port Status Register
1Ah
Port Status Register Latched
1Ch
Port Status Register Interrupt Enable
1Eh
Unused
Register Name:
PORT.CR1
Register Description:
Port Control Register 1
Register Address:
n * 80h + 00h
Bit #
15
14
13
12
11
10
9
8
Name
Default
0
Bit #
7
6
5
4
3
2
1
0
Name
TMEI
MEIMS
PMUM
PMU
TPD
RPD
RSTDP
RST
Default
0
1
0
Bit 7: Transmit Manual Error Insert (TMEI).
When PORT.CR1:MEIMS = 0, this bit is used to insert errors in all
blocks where block-level MEIMS = 1. Error(s) are inserted at the next opportunity after this bit transitions from low
to high. See Section 8.7.5. Note: This bit should be set low immediately after each error insertion.
Bit 6: Transmit Manual Error Insert Mode Select (MEIMS).
This bit specifies the source of the error insertion
signal for all block-level error generators that have block-level MEIMS = 1. See Section 8.7.5.
0 = Port-level error insertion via PORT.CR1:TMEI
1 = Global error insertion as specified by GLOBAL.CR1:MEIMS
Bit 5: Port Performance Monitor Update Mode (PMUM).
This bit specifies the source of the performance
monitoring update signal for all blocks that have block-level PMUM = 1. See Section 8.7.4.
0 = Port-level PM update via PORT.CR1:PMU
1 = Global PM update as specified by GLOBAL.CR1:GPM[1:0]
Bit 4: Port Performance Monitor Register Update (PMU).
When PORT.CR1:PMUM = 0, this bit is used to
update all of the performance monitor registers where block-level PMUM = 1. When this bit transitions from low to
high, all configured performance monitoring registers are updated with the latest counter values, and all associated
counters are reset. This bit should remain high until the performance monitor update status bit (PORT.SR:PMS)
goes high, and then it should be brought back low, which clears the PMS status bit. If a counter increment occurs
at the exact same time as the counter reset, the counter is loaded with a value of one, and the “counter is non-
zero” latched status bit is set. See Section 8.7.4.
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