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| 型號(hào)： | DS32506N+ |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 70/130頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU DS3/E3/STS-1 484-BGA |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 類型： | 線路接口裝置（LIU） |
| 規(guī)程： | IEEE 1149.1 |
| 電源電壓： | 1.8V, 3.3V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 484-BGA |
| 供應(yīng)商設(shè)備封裝： | 484-BGA（23x23） |
| 包裝： | 管件 |
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DS32506/DS32508/DS32512
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8.8.5 Clear-On-Read And Clear-On-Write Modes
The latched status register bits can be programmed to clear on a read access or clear on a write access. The
global control register bit GLOBAL.CR2.LSBCRE specifies the method used to clear all of the latched status
registers. When LSBCRE = 0, latched status register bits are cleared when written with a 1. When LSBCRE = 1,
latched status register bits are cleared when read.
The clear-on-write mode expects the user to use the following method: read the latched status register then write a
1 to the register bits to be cleared. This method is useful when multiple software tasks use the same latched status
register. Each task can clear the bits it uses without affecting any of the latched status bits used by other tasks.
The clear-on-read mode clears all latched status bits in a register automatically when the latched status register is
read. This method works well when no more than one software task uses any single latched status register. An
event that occurs while the associated latched status register is being read results in the associated latched status
bit being set after the read is completed.
8.8.6 Global Write Mode
When GLOBAL.CR2:GWRM = 1, a write to a register of any port causes the data to be written to the same register
in all the ports on the device. In this mode register reads are not supported and result in undefined data.
8.9 SPI Serial Microprocessor Interface
When the IFSEL pins are set to 01X the device presents an SPI interface on the CS, SCLK, SDI, and SDO pins.
SPI is a widely-used master/slave bus protocol that allows a master device and one or more slave devices to
communicate over a serial bus. The DS325xx is always a slave device. Masters are typically microprocessors,
ASICs or FPGAs. Data transfers are always initiated by the master device, which also generates the SCLK signal.
The DS325xx receives serial data on the SDI pin and transmits serial data on the SDO pin. SDO is high-impedance
except when the DS325xx is transmitting data to the bus master. Note that the ALE pin must be wired high for
proper operation of the SPI interface.
Bit Order.
When IFSEL[2:0] = 010 the register address and all data bytes are transmitted MSB first on both SDI
and SDO. When IFSEL[2:0] = 011, the register address and all data bytes are transmitted LSB first on both SDI
and SDO. The Motorola SPI convention is MSB first.
Clock Polarity and Phase.
and pulses high during bus transactions. When CPOL = 1, SCLK is normally high and pulses low during bus
transactions. The CPHA pin sets the phase (active edge) of SCLK. When CPHA = 0, data is latched in on SDI on
the leading edge of the SCLK pulse and updated on SDO on the trailing edge. When CPHA = 1, data is latched in
on SDI on the trailing edge of the SCLK pulse and updated on SDO on the following leading edge. See Figure
Device Selection.
Each SPI device has its own chip-select line. To select the DS325xx, pull its CS pin low.
Control Word.
After CS is pulled low, the bus master transmits the control word during the first 16 SCLK cycles. In
MSB-first mode, the control word has the form:
R/W A13 A12 A11 A10 A9 A8 A7
A6 A5 A4 A3 A2 A1 A0 BURST
where A[13:0] is the register address, R/
W is the data direction bit (1 = read, 0 = write), and BURST is the burst bit
(1 = burst access, 0 = single-byte access). In LSB-first mode, the order of the 14 address bits is reversed. In the
discussion that follows, a control word with R/
W = 1 is a read control word, while a control word with R/W = 0 is a
write control word. Note: The address range of the DS32512 is 000h–7FFh, so A[13:11] are ignored.
Single-Byte Writes.
See Figure 8-11. After CS goes low, the bus master transmits a write control word with
BURST = 0 followed by the data byte to be written. The bus master then terminates the transaction by pulling
high.
Single-Byte Reads.
See Figure 8-11. After CS goes low, the bus master transmits a read control word with
BURST = 0. The DS325xx then responds with the requested data byte. The bus master then terminates the
transaction by pulling
CS high.
Burst Writes.
See Figure 8-11. After CS goes low, the bus master transmits a write control word with BURST = 1
followed by the first data byte to be written. The DS325xx receives the first data byte on SDI, writes it to the
specified register, increments its internal address register, and prepares to receive the next data byte. If the master
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS32506N# | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 6-Port DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS32506N+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 6-Port DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS32506NA2 | 制造商:Maxim Integrated Products 功能描述:DS32506A2 X6 DS3/E3 LIU - Rail/Tube |
| DS32506NW | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS32506W | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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