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__________________________________________________________________________________________DS26900
41
9.3
JTAG Instruction Register and Instructions
The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. When the
TAP controller enters the Shift-IR state, the instruction shift register is connected between PTDI and PTDO. While
in the Shift-IR state, a rising edge on PTCLK with PTMS low shifts data one stage towards the serial output at
PTDO. A rising edge on PTCLK in the Exit1-IR state or the Exit2-IR state with PTMS high moves the controller to
the Update-IR state. The falling edge of that same PTCLK latches the data in the instruction shift register to the
instruction parallel output. Instructions supported by the DS26900 and their respective operational binary codes are
Table 9-1. Periphery JTAG Instruction Codes
INSTRUCTIONS
SELECTED REGISTER
INSTRUCTION CODES
SAMPLE/PRELOAD
Boundary Scan
010
BYPASS
Bypass
111
EXTEST
Boundary Scan
000
CLAMP
Bypass
011
HIGHZ
Bypass
100
IDCODE
Device Identification
001
9.3.1 SAMPLE/PRELOAD
This is a mandatory instruction for the IEEE 1149.1 specification. This instruction supports two functions. The
digital I/Os of the device can be sampled at the boundary scan register without interfering with the normal operation
of the device by using the Capture-DR state. SAMPLE/PRELOAD also allows the DS26900 to shift data into the
boundary scan register via PTDI using the Shift-DR state.
9.3.2 EXTEST
EXTEST allows testing of all interconnections to the device. When the EXTEST instruction is latched in the
instruction register, the following actions occur. Once enabled via the Update-IR state, the parallel outputs of all
digital output pins are driven. The boundary scan register is connected between PTDI and PTDO. The Capture-DR
samples all digital inputs into the boundary scan register.
9.3.3 BYPASS
When the BYPASS instruction is latched into the parallel Instruction register, PTDI connects to PTDO through the
1-bit bypass test register. This allows data to pass from PTDI to PTDO not affecting the device's normal operation.
9.3.4 IDCODE
When the IDCODE instruction is latched into the parallel Instruction register, the identification test register is
selected. The device identification code is loaded into the Identification register on the rising edge of PTCLK
following entry into the Capture-DR state. Shift-DR can be used to shift the identification code out serially via
PTDO. During Test-Logic-Reset, the identification code is forced into the instruction register's parallel output. The
device ID code always has a one in the LSB position. The next 11 bits identify the manufacturer's JEDEC number
and number of continuation bytes followed by 16 bits for the device and 4 bits for the version. The device ID code
for the DS26900 is 0008D143.
9.3.5 HIGHZ
All digital outputs are placed into a high-impedance state. The bypass register is connected between PTDI and
PTDO.