參數(shù)資料
型號(hào)： DS26900LN+
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 22/49頁(yè)
文件大?。?/td> 0K
描述： IC JTAG MUX/SWITCH 144-LQFP
標(biāo)準(zhǔn)包裝： 90
系列： *
功能： *
電壓電源： 單電源
電壓 - 電源，單路/雙路(±)： 3.14 V ~ 3.47 V
電流 - 電源： *
工作溫度： *
安裝類(lèi)型： 表面貼裝
封裝/外殼： 144-LQFP
供應(yīng)商設(shè)備封裝： 144-LQFP（20x20）
包裝： 托盤(pán)
__________________________________________________________________________________________DS26900
29
The MSB of the instruction code acts as an address bit. When in cascade configuration, the cascade master’s TDO
output and port communications is enabled only when the instruction MSB is 0. The cascade extension’s TDO
output and port communications is enabled only when the instruction MSB is 1. In Single-Package Mode, TDO
output and port communications is enabled only when the instruction MSB is 0.
6.1.1.1 IDCODE
The IDCODE instruction allows access to the ID Register (IDR). The IDR register is an 8-bit read-only register that
contains the revision code for the DS26900 in the lower 4 bits and a fixed 4-bit code in the upper 4 bits. This is
identical to the revision code of the ID code, which is used for the periphery boundary scan. The IDR register is
read-only. Writes to this register are ignored.
6.1.1.2 PORT_DET
The PORT_DET instruction initiates the sensing of the presence of secondary ports and allows access to the 20-bit
Port Detection Register (PDR). The process of port detection temporarily changes the STMSn bidirectional pin
outputs to inputs, senses which ports read as logical 1 (ports should have a 10k
resistive pullup on their STMSn
pin and the DS26900 has a 20k
pulldown), and saves the results to the PDR register. Then the user must wait in
the Run-Test-Idle state for a period of time to allow the voltage on the STMS pin to settle, typically 100ms. A “1” in
a bit position indicates that logic 1 was sensed on that port’s STMS pin. However, due to implementation variables,
logic 0 in a bit position does not necessarily imply that a device is not attached to that port (the port STMS pin must
have a pullup on STMS in order to be sensed). The PDR register inputs are level sensitive and are sampled after
the PORT_DET instruction is loaded. The values in this register do not affect the operation of the DS26900. Port
detection works for single-package and the two-package cascade configuration. Writes to this register are ignored.
6.1.1.3 PORT_SEL
The PORT_SEL instruction allows access to the 5-bit read/write Secondary Port Selection Register (SPSR).
Writing a value to this register selects a port with which to communicate. Valid addresses are from 00001b (port
one selected) to 10100b (TMS2). Addresses greater than 10100b and address 00000b do not select a port.
Selecting an empty or nonexistent port has no adverse effect on the device, and no secondary port signals will
toggle.
6.1.1.4 GPIO_CFG
The GPIO_CFG instruction allows access to the 8-bit read/write GPIO Configuration and Write Register (GPIOCR).
The four GPIO pins can be individually configured to be an input, output logic 1, or output logic 0. The values,
which are sensed on the pins, are available in the GPIO Read Register (GPIORR) via the GPIO_READ instruction.
After global reset, the GPIO Configuration and Write Register (GPIOCR) bits are set to 00000000b and the GPIO
pins are set to input mode.
6.1.1.5 GPIO_READ
The GPIO_READ instruction allows access to the 4-bit read-only GPIO Read Register (GPIORR). A “1” in a bit
position indicates that logic 1 was sensed on that input’s GPIO pin, and a “0” in a bit position indicates that logic 0
was sensed on that GPIO pin. If a pin was configured as an output, the register bit indicates the value being output.
Writes to this register are ignored.
The GPIO inputs are level sensitive and are sampled after the GPIO_READ instruction is loaded. GPIO pins that
are configured as outputs are always read in this register as the value that is being output. After reset, the GPIO
Read Register (GPIORR) bits are set to 0000b until a GPIO_READ instruction is given. Writes to this register are
ignored.
6.1.1.6 CONFIG
The CONFIG instruction allows access to the 6-bit read/write Device Configuration Register (DCR). The DCR
register controls options such as path and signaling inversions and the default deselected port drive values.
6.1.1.7 SCRATCH_1
The SCRATCH_1 instruction allows access to the 32-bit read/write Scratchpad 1 Register (SPR1). The SPR1
register is a user storage location, which is reset by the global reset signal. The values stored in this register do not
affect the operation of the DS26900.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS26900LN+ 功能描述:多路器開(kāi)關(guān) IC JTAG MUX RoHS:否 制造商:Texas Instruments 通道數(shù)量:1 開(kāi)關(guān)數(shù)量:4 開(kāi)啟電阻（最大值）:7 Ohms 開(kāi)啟時(shí)間（最大值）: 關(guān)閉時(shí)間（最大值）: 傳播延遲時(shí)間:0.25 ns 工作電源電壓:2.3 V to 3.6 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UQFN-16
DS26900N+ 制造商:MAXIM 制造商全稱(chēng):Maxim Integrated Products 功能描述:JTAG Multiplexer/Switch
DS26C31 制造商:NSC 制造商全稱(chēng):National Semiconductor 功能描述:CMOS QUAD TRI-STATE DIFFERENTIAL LINE DRIVER
DS26C31 DIE 制造商:Texas Instruments 功能描述:
DS26C31_BBA3026X WAF 制造商:Texas Instruments 功能描述:
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