參數(shù)資料
型號(hào): DS26504LNB2+
廠商: Maxim Integrated Products
文件頁數(shù): 33/129頁
文件大?。?/td> 0K
描述: IC T1/E1/J1 64KCC ELEMENT 64LQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 160
功能: BITS 元件
接口: 64KCC,E1,T1
電路數(shù): 1
電源電壓: 3.14 V ~ 3.47 V
電流 - 電源: 150mA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-LQFP(10x10)
包裝: 管件
包括: *
其它名稱: 90-26504+NB2
DS26504 T1/E1/J1/64KCC BITS Element
128 of 129
21. REVISION HISTORY
REVISION
DATE
DESCRIPTION
PAGES
CHANGED
070105
New product release.
081105
Corrected the polarity of the TAIS pin when operating in Hardware mode.
19, 29
101805
Changed Section 13.4 to read “2.048 x 2N (where N = 1 to 3)” instead of
“2.048 x N (where N = 1 to 4).”
020906
Section 13.3.1, Section 13.3.2, SR1 Bits 1 and 2: Clarified the open circuit and
short circuit wording.
Figure 13-1: Corrected the capacitor value from 1
μF to 10μF.
Replaced Figure 13-4 and 13-5 (added Table 13-1 and Table 13-2) to show
two different types of recommended protection circuit interfaces.
Added package drawing link to Package Information section, along with
updated package drawing.
Removed reference to E1RCR and E1TCR bit 3 (this bit functionality has been
moved to the MCREG).
48
053107
Replaced Figure 13-4 and Figure 13-5 to show 10
μF cap on TTIP.
92, 93
100507
In the Absolute Maximum Ratings (Section 19), added Note 1: Specifications
at -40
°C are guaranteed by design GBD and not production tested. to
Operating Temp Range for DS26504LN. Renumbered notes for Table 19-1 to
Table 19-5.
113, 114
Clarified RITD and TITD descriptions.
16, 17
For E1TS description, changed 0 = 120
Ω and 1 = 75Ω to 0 = 75Ω and 1 =
120
Ω.
19
121707
Corrected Note 2 in the LIC1[7:5] register description to include TT2 along
with TT0 and TT1.
84
042208
In Section 13, corrected the wording to clearly indicate that different
transformers are required for T1, J1, E1, and 6312kHz modes and for 64KCC
mode.
79
072308
In Table 7-2, changed address 21 and 22 from “—” to “SR5” and “IMR5”;
added bit 4 (SR5) to IIR.
32, 39
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