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參數(shù)資料
| 型號(hào)： | DS26324GNA2+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 49/120頁 |
| 文件大小： | 0K |
| 描述： | IC INTERFACE LINE 16CH 256-CSBGA |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 40 |
| 類型： | 線路接口裝置（LIU） |
| 驅(qū)動(dòng)器/接收器數(shù)： | 16/16 |
| 規(guī)程： | LIN |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 256-LBGA，CSBGA |
| 供應(yīng)商設(shè)備封裝： | 256-CSBGA（17x17） |
| 包裝： | 托盤 |
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DS26324 3.3V, 16-Channel, E1/T1/J1 Short-Haul Line Interface Unit
34 of 120
5.9
BERT
There are two bit error-rate testers available on the DS26324. One BERT can be mapped into LIUs 1–8 and the
other into LIUs 9–16 via the BTCR registers. The two BERTs operate independently of each other.
Each BERT transmitter, by default, replaces data from TPOS and TNEG; each BERT receiver, by default, samples
recovered data from RTIP and RRING.
The BERT can be enabled to replace data received on RTIP and RRING via the BERTDIR bit in the BERT and
G.772 Monitoring Control Register (BGMC). In this mode, the SRMS bit determines whether data comes out single-
rail or dual-rail. BERT data can be sourced using the recovered clock, MCLK, or TCLK. In this mode of operation,
the BERT receiver samples data on TPOS and TNEG on the falling edge of TCLK. This function is useful for
testing the digital side of the LIU. If TCLK is selected as a source for this mode, the input TCLK will control the
BERT transmitter and receiver. If the recovered clock or MCLK is selected, the RCLK output needs to drive the
TCLK input in order for the BERT receiver to sync to the data.
5.9.1
General Description
The BERT is a software-programmable test pattern generator and monitor capable of meeting most error
performance requirements for digital transmission equipment. It will generate and synchronize to pseudorandom
patterns with a generation polynomial of the form x
n + xy + 1, where n and y can take on values from 1 to 32 and
repetitive patterns of any length up to 32 bits.
The transmit direction generates the programmable test pattern, and inserts the test pattern payload into the data
stream.
The receive direction extracts the test pattern payload from the receive data stream, and monitors the test pattern
payload for the programmable test pattern.
5.9.1.1
BERT Features
Programmable PRBS Pattern. The pseudorandom bit sequence (PRBS) polynomial (x
n + xy + 1) and
seed are programmable (length n = 1 to 32, tap y = 1 to n – 1, and seed = 0 to 2
n – 1).
Programmable Repetitive Pattern. The repetitive pattern length and pattern are programmable (the
length n = 1 to 32 and pattern = 0 to 2
n – 1).
24-Bit Error Count and 32-Bit Bit Count Registers
Programmable Bit-Error Insertion. Errors can be inserted individually, on a pin transition, or at a specific
rate. The rate 1/10
n is programmable (n = 1 to 7).
Pattern Synchronization at a 10
-3 BER. Pattern synchronization is achieved even in the presence of a
random bit error rate (BER) of 10
-3.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS26324GNA2+ | 功能描述:電信集成電路 RoHS:否 制造商:STMicroelectronics 類型:Telecom IC - Various 工作電源電壓:4.75 V to 5.25 V 電源電流: 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-100 封裝:Tray |
| DS26324GNA2+W | 制造商:Maxim Integrated Products 功能描述:FRAMER E1/J1/T1 3.3V 256PIN TE-CSBGA - Rail/Tube |
| DS26324GNA3 | 功能描述:電信集成電路 3.3V E1/T1/J1 16Ch Short Haul Octal LIU RoHS:否 制造商:STMicroelectronics 類型:Telecom IC - Various 工作電源電壓:4.75 V to 5.25 V 電源電流: 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-100 封裝:Tray |
| DS26324GNA3+ | 功能描述:電信集成電路 3.3V E1/T1/J1 16Ch Short Haul Octal LIU RoHS:否 制造商:STMicroelectronics 類型:Telecom IC - Various 工作電源電壓:4.75 V to 5.25 V 電源電流: 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-100 封裝:Tray |
| DS26324N | 制造商:Maxim Integrated Products 功能描述:DS26324 X16 T1E1J1 LIU S-HAUL IND - Rail/Tube |
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