參數(shù)資料
型號(hào): DS2490S
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: Bus Controller
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PDSO24
封裝: 0.300 INCH, SO-24
文件頁數(shù): 48/51頁
文件大?。?/td> 444K
代理商: DS2490S
DS2490
6 of 50
or lower should be used. If the fall time is shorter, a parameter code of 0x5 or higher should be used.
Once determined, the value code for the PULLDOWN SLEW RATE control parameter should be stored
in the host and always be loaded into the DS2490 after a power-on or master reset cycle.
1-WIRE TIMING DIAGRAMS
This section explains the 1-Wire bus waveforms generated by the DS2490. First, the communication
waveforms such as the reset/presence detect sequence and read/write data time slots are discussed
followed by a detailed description of the Pulse function under various conditions.
1-Wire Communication Wave Forms
One of the major features of the DS2490 is that it relieves the host from generating the timing of the 1-
Wire signals and sampling the 1-Wire bus at the appropriate times. The reset/presence detect sequence is
shown in Figure 5. This sequence is composed of four timing segments: the reset low time tRSTL, the
short/interrupt sampling offset tSI, the presence detect sampling offset tPDT and a delay time tFILL. The
timing segments tSI, tPDT and tFILL comprise the reset high time tRSTH where 1-Wire slave devices assert
their presence or interrupt pulse. During this time, the DS2490 pulls the 1-Wire bus high with a weak
pullup current.
Reset/presence timing values are shown in Figure 5. The values of all timing segments for all 1-Wire
speed options are shown in the table. Since the reset/presence sequence is slow compared to the time
slots, the values for regular and flexible speed are the same. Except for the falling edge of the presence
pulse, all edges are controlled by the DS2490. The shape of the uncontrolled falling edge is determined
by the capacitance of the 1-Wire bus and the number, speed, and sink capability of the slave devices
connected.
RESET/PRESENCE DETECT Figure 5
NOMINAL TIMING VALUES
SPEED
t
RSTL
t
SI
t
PDT
t
FILL
t
RSTH
REGULAR
512s
8s
64s
512s
584s
OVERDRIVE
64s
2s
8s
64s
74s
FLEXIBLE
512s
8s
64s
512s
584s
Upon executing a 1-WIRE RESET command (see COMMUNICATION COMMANDS), the DS2490
pulls the 1-Wire bus low for tRSTL and then lets it go back to 5V. The DS2490 will now wait for the
short/interrupt sampling offset tSI to expire and then test the voltage on the 1-Wire bus to determine if
there is a short or an interrupt signal. If there is no short or interrupt the DS2490 will wait for tPDT and test
the voltage on the 1-Wire bus for a presence pulse. Regardless of the result of the presence test, the
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