![](http://datasheet.mmic.net.cn/Maxim-Integrated-Products/DS2483Q-T_datasheet_97048/DS2483Q-T_4.png)
4
Maxim Integrated
DS2483
Single-Channel 1-Wire Master
with Adjustable Timing and Sleep Mode
Note 1: Limits are 100% production tested at TA = +25°C and/or TA = +85°C. Limits over the operating temperature range and
relevant supply voltage range are guaranteed by design and characterization. Typical values are not guaranteed.
Note 2: The VCI2C voltage is applied at the SLPZ pin. VCI2C must always be < VCC. The DS2483 measures VCI2C after tSWUP
(wakeup from sleep mode) or after tOSCWUP (power-on reset). The Device Reset command does not cause the DS2483 to measure VCI2C.
Note 3: The active pullup does not apply to the rising edge of a presence pulse outside of a
1-Wire Reset command or during the
recovery after a short on the 1-Wire line.
Note 4: Guaranteed design and not production tested.
Note 5: Except for tF1, all 1-Wire timing specifications are derived from the same timing circuit.
Note 6: Although 1-Wire slave data sheets specify a tW1L and tRL minimum of 1s, 1-Wire slaves will accept the shorter 0.71s
tW1L and tRL of the DS2483.
Note 7: VCCACT refers to the VCC level being applied in the application.
Note 8: I2C communication should not take place for the max tOSCWUP or tSWUP time following a power-on reset or a wake-up
from sleep mode.
Note 9: All I2C timing values are referenced to VIH(MIN) and VIL(MAX) levels.
Note 10: The DS2483 does not obstruct the SDA and SCL lines if SLPZ is at 0V or if VCC is switched off.
Note 11: The DS2483 provides a hold time of at least 300ns for the SDA signal (referenced to the VIH(MIN) of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
Note 12: The maximum tHD:DAT must only be met if the device does not stretch the low period (tLOW) of the SCL signal.
Note 13: A fast mode I2C bus device can be used in a standard mode I2C bus system, but the requirement tSU:DAT R 250ns
must then be met. This requirement is met since the DS2483 does not stretch the low period of the SCL signal. Also the
acknowledge timing must meet this setup time (I2C bus specification Rev. 03, 19 June 2007).
Note 14: CB = Total capacitance of one bus line in pF. The maximum bus capacitance allowable can vary from this value depend-
ing on the actual operating voltage and frequency of the application (I2C bus specification Rev. 03, 19 June 2007).
ELECTRICAL CHARACTERISTICS (continued)
(TA = -40NC to +85NC, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input Current with Input Voltage
Between 0.1 O VCC(MAX) and 0.9
O
VCC(MAX)
II
(Note 10)
-10
+10
F
A
Input Capacitance
CI
(Note 4)
10
pF
SCL Clock Frequency
fSCL
0
400
kHz
Hold Time (Repeated) START
Condition (After this period, the
first clock pulse is generated.)
tHD:STA
0.6
F
s
Low Period of the SCL Clock
tLOW
1.3
F
s
High Period of the SCL Clock
tHIGH
0.6
F
s
Setup Time for a Repeated
START Condition
tSU:STA
0.6
F
s
Data Hold Time
tHD:DAT
(Notes 11, 12)
0.9
F
s
Data Setup Time
tSU:DAT
(Note 13)
250
ns
Setup Time for STOP Condition
tSU:STO
0.6
F
s
Bus Free Time Between a STOP
and START Condition
tBUF
1.3
F
s
Capacitive Load for Each Bus
Line
CB
(Notes 4, 14)
400
pF
Oscillator Warmup Time
tOSCWUP (Notes 4, 8)
2
ms