參數(shù)資料
型號(hào): DS21FT44N+
廠商: Maxim Integrated Products
文件頁數(shù): 106/117頁
文件大小: 0K
描述: IC FRAMER 4X4 16CH 300-BGA
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 40
控制器類型: E1 調(diào)幀器
接口: 并行/串行
電源電壓: 2.97 V ~ 3.63 V
電流 - 電源: 225mA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 300-BBGA
供應(yīng)商設(shè)備封裝: 300-PBGA(27x27)
包裝: 管件
DS21FT44/DS21FF44
89 of 117
21.4. TEST REGISTERS
IEEE 1149.1 requires a minimum of two test registers; the bypass register and the boundary scan register.
An optional test register has been included with the DS21Q44 design. This test register is the
identification register and is used in conjunction with the IDCODE instruction and the Test-Logic-Reset
state of the TAP controller.
Boundary Scan Register
This register contains both a shift register path and a latched parallel output for all control cells and
digital I/O cells and is 126 bits in length. able 21-3 shows all of the cell bit locations and definitions.
Bypass Register
This is a single 1-bit shift register used in conjunction with the BYPASS, CLAMP, and HIGH-Z
instructions, which provides a short path between JTDI and JTDO.
Identification Register
The identification register contains a 32-bit shift register and a 32 bit latched parallel output. This register
is selected during the IDCODE instruction and when the TAP controller is in the Test-Logic-Reset state.
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