參數(shù)資料
型號： DS21FT44N+
廠商： Maxim Integrated Products
文件頁數(shù)： 105/117頁
文件大?。?/td> 0K
描述： IC FRAMER 4X4 16CH 300-BGA
產品培訓模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝： 40
控制器類型： E1 調幀器
接口： 并行/串行
電源電壓： 2.97 V ~ 3.63 V
電流 - 電源： 225mA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 300-BBGA
供應商設備封裝： 300-PBGA（27x27）
包裝： 管件
DS21FT44/DS21FF44
88 of 117
SAMPLE/PRELOAD
A mandatory instruction for the IEEE 1149.1 specification. This instruction supports two functions. The
digital I/Os of the DS21Q44 can be sampled at the boundary scan register without interfering with the
normal operation of the device by using the Capture-DR state. SAMPLE/PRELOAD also allows the
DS21Q44 to shift data into the boundary scan register by JTDI using the Shift-DR state.
EXTEST
EXTEST allows testing of all interconnections to the DS21Q44. When the EXTEST instruction is
latched in the instruction register, the following actions occur. Once enabled by the Update-IR state, the
parallel outputs of all digital output pins will be driven. The boundary scan register will be connected
between JTDI and JTDO. The Capture-DR will sample all digital inputs into the boundary scan register.
BYPASS
When the BYPASS instruction is latched into the parallel instruction register, JTDI connects to JTDO
through the 1 bit bypass test register. This allows data to pass from JTDI to JTDO not affecting the
device’s normal operation.
IDCODE
When the IDCODE instruction is latched into the parallel instruction register, the Identification Test
register is selected. The device identification code will be loaded into the Identification register on the
rising edge of JTCLK following entry into the Capture-DR state. Shift-DR can be used to shift the
identification code out serially by JTDO. During Test-Logic-Reset, the identification code is forced into
the instruction register’s parallel output. The ID code will always have a ‘1’ in the LSB position. The
next 11 bits identify the manufacturer’s JEDEC number and number of continuation bytes followed by 16
bits for the device and 4 bits for the version. See Table 21-2. Table 21-3 lists the device ID codes for the
DS21Q42 and DS21Q44 devices.
Table 21-2. ID CODE STRUCTURE
MSB
LSB
CONTENTS
Version
(Contact Factory)
Device ID
(See Table 21-3)
JEDEC
“00010100001”
“1”
LENGTH
4 bits
16 bits
11 bits
1 bit
Table 21-3. DEVICE ID CODES
DEVICE
16-BIT NUMBER
DS21Q42
0000h
DS21Q44
0001h
HIGH-Z
All digital outputs of the DS21Q44 will be placed in a high impedance state. The BYPASS register will
be connected between JTDI and JTDO.
CLAMP
All digital outputs of the DS21Q44 will output data from the boundary scan parallel output while
connecting the bypass register between JTDI and JTDO. The outputs will not change during the CLAMP
instruction.
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相關代理商/技術參數(shù)
參數(shù)描述
DS21FT44N+ 功能描述:網(wǎng)絡控制器與處理器 IC 4x4 16/4x3 12 Chnl E1/E1 Framer RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21Q348 功能描述:網(wǎng)絡控制器與處理器 IC RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21Q348B 功能描述:網(wǎng)絡控制器與處理器 IC RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21Q348DK 功能描述:網(wǎng)絡開發(fā)工具 RoHS:否 制造商:Rabbit Semiconductor 產品:Development Kits 類型:Ethernet to Wi-Fi Bridges 工具用于評估:RCM6600W 數(shù)據(jù)速率:20 Mbps, 40 Mbps 接口類型:802.11 b/g, Ethernet 工作電源電壓:3.3 V
DS21Q348N 功能描述:網(wǎng)絡控制器與處理器 IC RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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