參數(shù)資料
型號(hào): DS21FF44
廠商: DALLAS SEMICONDUCTOR
元件分類: Digital Transmission Controller
英文描述: DATACOM, FRAMER, PBGA300
封裝: 27 X 27 MM, 1.27 MM PITCH, MCMBGA-300
文件頁(yè)數(shù): 92/110頁(yè)
文件大小: 526K
代理商: DS21FF44
DS21FT44/DS21FF44
82 of 110
21.4. TEST REGISTERS
IEEE 1149.1 requires a minimum of two test registers; the bypass register and the boundary scan register.
An optional test register has been included with the DS21Q44 design. This test register is the
identification register and is used in conjunction with the IDCODE instruction and the Test-Logic-Reset
state of the TAP controller.
Boundary Scan Register
This register contains both a shift register path and a latched parallel output for all control cells and
digital I/O cells and is 126 bits in length. Table 21-3 shows all of the cell bit locations and definitions.
Bypass Register
This is a single 1 bit shift register used in conjunction with the BYPASS, CLAMP, and HIGHZ
instructions, which provides a short path between JTDI and JTDO.
Identification Register
The identification register contains a 32-bit shift register and a 32 bit latched parallel output.
This
register is selected during the IDCODE instruction and when the TAP controller is in the Test-Logic-
Reset state.
Boundary Scan Register Description Table 21-4
MCM
LEAD
(DIE1)
MCM
LEAD
(DIE2)
MCM
LEAD
(DIE3)
MCM
LEAD
(DIE4)
SCAN
REGIST
ER BIT
DS21Q42
DIE
SYMBOL
TYPE
CONTROL
BIT
DESCRIPTION
B7
102
8MCLK
O
G20
60
A0
I
H20
59
A1
I
G19
58
A2
I
H19
57
A3
I
G18
56
A4
I
H18
55
A5
I
G17
54
A6/ALE (AS)
I
H17
37
A7
I
W15
22
BTS
I
-
94
BUS.cntl
-
0 = D0-D7 or
AD0-AD7 are
inputs
1 = D0-D7 or
AD0-AD7 are
outputs
B6
100
CLKSI
I
T8
Y4
Y15
E19
23
CS*
I
L20
93
D0 or AD0
I/O
M20
92
D1 or AD1
I/O
L19
91
D2 or AD2
I/O
M19
90
D3 or AD3
I/O
L18
89
D4 or AD4
I/O
M18
88
D5 or AD5
I/O
L17
87
D6 or AD6
I/O
相關(guān)PDF資料
PDF描述
DS21FF44N DATACOM, FRAMER, PBGA300
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