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    參數(shù)資料
    型號: DS21FF44
    廠商: DALLAS SEMICONDUCTOR
    元件分類: Digital Transmission Controller
    英文描述: DATACOM, FRAMER, PBGA300
    封裝: 27 X 27 MM, 1.27 MM PITCH, MCMBGA-300
    文件頁數(shù): 90/110頁
    文件大小: 526K
    代理商: DS21FF44
    DS21FT44/DS21FF44
    80 of 110
    TAP Controller State Machine Figure 21-2
    21.3. INSTRUCTION REGISTER AND INSTRUCTIONS
    The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length.
    When the TAP controller enters the Shift-IR state, the instruction shift register will be connected between
    JTDI and JTDO. While in the Shift-IR state, a rising edge on JTCLK with JTMS low will shift the data
    one stage towards the serial output at JTDO. A rising edge on JTCLK in the Exit1-IR state or the Exit2-
    IR state with JTMS high will move the controller to the Update-IR state The falling edge of that same
    JTCLK will latch the data in the instruction shift register to the instruction parallel output. Instructions
    supported by the DS21Q44 with their respective operational binary codes are shown in Table 21-1.
    Instruction Codes For The DS21Q44 IEEE 1149.1 Architecture Table 21-1
    Instruction
    Selected Register
    Instruction Code
    SAMPLE/PRELOAD
    Boundary Scan
    010
    BYPASS
    Bypass
    111
    EXTEST
    Boundary Scan
    000
    CLAMP
    Boundary Scan
    011
    HIGHZ
    Boundary Scan
    100
    IDCODE
    Device Identification
    001
    1
    0
    1
    11
    1
    11
    1
    00
    0
    1
    0
    1
    0
    Select
    DR-Scan
    Capture DR
    Shift DR
    Exit DR
    Pause DR
    Exit2 DR
    Update DR
    Select
    IR-Scan
    Capture IR
    Shift IR
    Exit IR
    Pause IR
    Exit2 IR
    Update IR
    Test Logic
    Reset
    Run Test/
    Idle
    0
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