參數(shù)資料
型號: DS21FF44
廠商: DALLAS SEMICONDUCTOR
元件分類: Digital Transmission Controller
英文描述: DATACOM, FRAMER, PBGA300
封裝: 27 X 27 MM, 1.27 MM PITCH, MCMBGA-300
文件頁數(shù): 36/110頁
文件大?。?/td> 526K
代理商: DS21FF44
DS21FT44/DS21FF44
31 of 110
ADDRESS
R/W
REGISTER NAME
REGISTER ABBREVIATION
9C
R/W
Receive Channel 29
RC29
9D
R/W
Receive Channel 30
RC30
9E
R/W
Receive Channel 31
RC31
9F
R/W
Receive Channel 32
RC32
A0
R/W
Transmit Channel Control 1
TCC1
A1
R/W
Transmit Channel Control 2
TCC2
A2
R/W
Transmit Channel Control 3
TCC3
A3
R/W
Transmit Channel Control 4
TCC4
A4
R/W
Receive Channel Control 1
RCC1
A5
R/W
Receive Channel Control 2
RCC2
A6
R/W
Receive Channel Control 3
RCC3
A7
R/W
Receive Channel Control 4
RCC4
A8
R/W
Common Control 4
CCR4
A9
R
Transmit DS0 Monitor
TDS0M
AA
R/W
Common Control 5
CCR5
AB
R
Receive DS0 Monitor
RDS0M
AC
R/W
Test 3
TEST3 (set to 00H)
AD
Not used
(set to 00H)
AE
Not used
(set to 00H)
AF
Not used
(set to 00H)
B0
R/W
HDLC Control Register
HCR
B1
R/W
HDLC Status Register
HSR
B2
R/W
HDLC Interrupt Mask Register
HIMR
B3
R/W
Receive HDLC Information Register
RHIR
B4
R/W
Receive HDLC FIFO Register
RHFR
B5
R/W
Interleave Bus Operation Register
IBO
B6
R/W
Transmit HDLC Information Register
THIR
B7
R/W
Transmit HDLC FIFO Register
THFR
B8
R/W
Receive HDLC DS0 Control
Register 1
RDC1
B9
R/W
Receive HDLC DS0 Control
Register 2
RDC2
BA
R/W
Transmit HDLC DS0 Control
Register 1
TDC1
BB
R/W
Transmit HDLC DS0 Control
Register 2
TDC2
BC
Not used
(set to 00H)
BD
Not used
(set to 00H)
BE
Not used
(set to 00H)
BF
Not used
(set to 00H)
NOTES:
1. Test Registers 1, 2, and 3 are used only by the factory; these registers must be cleared (set to all
zeros) on power– up initialization to insure proper operation.
2. Register banks CxH, DxH, ExH, and FxH are not accessible.
相關(guān)PDF資料
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DS21FF44N DATACOM, FRAMER, PBGA300
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