參數(shù)資料
型號: DS1875T+T&R
廠商: Maxim Integrated Products
文件頁數(shù): 8/92頁
文件大?。?/td> 0K
描述: IC SFP CTRLR/TRIPLEXER 38-TQFN
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 2,500
應用: 光纖
接口: I²C
電源電壓: 2.85 V ~ 3.9 V
封裝/外殼: 38-WFQFN 裸露焊盤
供應商設備封裝: 38-TQFN(5x7)
包裝: 帶卷 (TR)
安裝類型: 表面貼裝
DS1875
PON Triplexer and SFP Controller
16
______________________________________________________________________________________
Detailed Description
The DS1875 integrates the control and monitoring func-
tionality required to implement a PON system using
Maxim’s MAX3643 compact burst-mode laser driver.
The compact laser-driver solution offers a considerable
cost benefit by integrating control and monitoring fea-
tures in the low-power CMOS process, while leaving
only the high-speed portions to the laser driver. Key
components of the DS1875 are shown in the
Block
Diagram and described in subsequent sections. Table
1 contains a list of acronyms used in this data sheet.
Bias Control
Bias current is controlled by an APC loop. The APC
loop uses digital techniques to overcome the difficulties
associated with controlling burst-mode systems.
Autodetect Bias Control
This is the default mode of operation. In autodetect bias
control, transmit burst length is monitored. A “short
burst” is declared when the burst is shorter than
expected based on the sample rate setting in Table
02h, Register 88h. In the case that 32 consecutive short
bursts are transmitted, the integrator is disabled and
the BIAS DAC is loaded from the BIAS LUT (Table 08h).
Any single burst of adequate burst length re-enables
the APC integrator.
Open-Loop Bias Control
Open-loop control is configured by setting FBOL in
Table 02h, Register C7h. In this mode, the BIAS LUT
(Table 08h) is directly loaded to the BIAS DAC output.
The BIAS LUT can be programmed in 2°C increments
over the 40°C to +102°C range. It is left-shifted so that
the LUT value is loaded to either the DAC MSB or the
DAC MSB-1 (Bit BOLFS, Table 02h, Register 89h).
Closed-Loop Bias Control
The closed-loop control requires a burst length long
enough to satisfy the sample rate settings in Table 02h,
Register 88h (APC_SR[3:0]). Closed-loop control is
configured by setting FBCL in Table 02h, Register C7h.
In this mode, the APC integrator is enabled, which con-
trols the BIAS DAC.
The APC loop begins by loading the value from the
BIAS LUT (Table 08h) indexed by the present tempera-
ture conversion. The feedback for the APC loop is the
monitor diode (BMD) current, which is converted to a
voltage using an external resistor. The feedback volt-
age is compared to an 8-bit scaleable voltage refer-
ence, which determines the APC set point of the
system. Scaling of the reference voltage accommo-
dates the wide range in photodiode sensitivities. This
allows the application to take full advantage of the APC
reference’s resolution.
The DS1875 has an LUT to allow the APC set point to
change as a function of temperature to compensate for
TE. The TE LUT (Table 05h) has 36 entries that deter-
mine the APC setting in 4°C windows between -40°C to
+100°C. Ranging of the APC DAC is possible by pro-
gramming a single byte in Table 02h, Register 8Dh.
Table 1. DS1875 Acronyms
ACRONYM
DEFINITION
10GEPON
10-Gigabit Ethernet PON
ADC
Analog-to-Digital Converter
AGC
Automatic Gain Control
APC
Automatic Power Control
APD
Avalanche Photodiode
BM
Burst Mode
BPON
Broadband PON
CATV
Cable Television
EPON
Ethernet PON
ER
Extinction Ratio
DAC
Digital-to-Analog Converter
FTTH
Fiber-to-the-Home
FTTX
Fiber-to-the-X
GEPON
Gigabit Ethernet PON
GPON
Gigabit PON
LOS
Loss of Signal
LUT
Lookup Table
TE
Tracking Error
TIA
Transimpedance Amplifier
ROSA
Receiver Optical Subassembly
RSSI
Receive Signal Strength Indicator
PON
Passive Optical Network
PWM
Pulse-Width Modulation
SFF
Small Form Factor
SFF-8472
Document Defining Register Map of
SFPs and SFFs
SFP
Small Form Factor Pluggable
SFP+
Enhanced SFP
TOSA
Transmit Optical Subassembly
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