參數資料
型號: DS1875T+T&R
廠商: Maxim Integrated Products
文件頁數: 42/92頁
文件大小: 0K
描述: IC SFP CTRLR/TRIPLEXER 38-TQFN
產品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 2,500
應用: 光纖
接口: I²C
電源電壓: 2.85 V ~ 3.9 V
封裝/外殼: 38-WFQFN 裸露焊盤
供應商設備封裝: 38-TQFN(5x7)
包裝: 帶卷 (TR)
安裝類型: 表面貼裝
DS1875
Lower Memory, Register 6Eh: STATUS
POWER-ON VALUE
X000 0XXXb
READ ACCESS
All
WRITE ACCESS
See below
MEMORY TYPE
Volatile
Write
Access
N/A
All
N/A
All
N/A
6Eh
FETG
STATUS
SOFT
FETG
RESERVED
TX-F
RESET
SOFT
TX-D
TX-F
STATUS
LOS
STATUS
RDYB
BIT 7
BIT 0
BIT 7
FETG STATUS: Reflects the active state of FETG. The FETG DIR bit in Table 02h, Register 89h
defines the polarity of FETG.
0 = Normal operation. Bias and modulation outputs are enabled.
1 = The FETG output is active. Bias and modulation outputs are disabled.
BIT 6
SOFT FETG:
0 = (Default)
1 = Forces the bias and modulation outputs to their off state and assert the FETG output.
BIT 5
RESERVED (Default = 0)
BIT 4
TX-F RESET:
0 = (Default)
1 = Resets the latch for the TX-F output. This bit is self-clearing after resetting TX-F.
BIT 3
SOFT TX-D: This bit allows a software control that is identical to the TX-D pin. See the BIAS and
MOD Output as a Function of Transmit Disable (TX-D) section for further information. Its value is
wired-ORed with the logic value of the TX-D pin.
0 = Internal TX-D signal is equal to the external TX-D pin.
1 = Internal TX-D signal is high.
BIT 2
TX-F STATUS: Reflects the active state of the TX-F pin.
0 = TX-F pin is not active.
1 = TX-F pin is active.
BIT 1
LOS STATUS: Loss of Signal. Reflects the logic level of the LOSI input pin.
0 = LOSI is logic-low.
1 = LOSI is logic-high.
BIT 0
RDBY: Ready Bar.
0 = VCC is above POA.
1 = VCC is below POA and/or too low to communicate over the I2C bus.
PON Triplexer and SFP Controller
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