參數(shù)資料
型號(hào)： DS1689SN+T&R
廠(chǎng)商： Maxim Integrated Products
文件頁(yè)數(shù)： 6/36頁(yè)
文件大小： 0K
描述： IC RTC SER NV RAM CTRL IN 28SOIC
標(biāo)準(zhǔn)包裝： 1,000
類(lèi)型： 時(shí)鐘/日歷
特點(diǎn)： NVSRAM
存儲(chǔ)容量： 114B
時(shí)間格式： HH:MM:SS（12/24 小時(shí)）
數(shù)據(jù)格式： YY-MM-DD-dd
接口： 并聯(lián)
電源電壓： 2.7 V ~ 3.3 V，4.5 V ~ 5.5 V
電壓 - 電源，電池： 2.5 V ~ 3.7 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 28-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 28-SOIC
包裝： 帶卷 (TR)
DS1689/DS1693
14 of 36
REGISTER B
MSB
LSB
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SET
PIE
AIE
UIE
SQWE
DM
24/12
DSE
Bit 7: SET. When the SET bit is 0, the update transfer functions normally by advancing the counts once
per second. When the SET bit is written to 1, any update transfer is inhibited and the program can
initialize the time and calendar bytes without an update occurring in the midst of initializing. Read cycles
can be executed in a similar manner. SET is a read/write bit that is not modified by internal functions of
the DS1689/DS1693.
Bit 6: PIE (Periodic Interrupt Enable). This bit is a read/write bit that allows the periodic interrupt flag
(PF) bit in Register C to drive the
IRQ pin low. When the PIE bit is set to 1, periodic interrupts are
generated by driving the
IRQ pin low at a rate specified by the RS3–RS0 bits of Register A. A 0 in the
PIE bit blocks the
IRQ output from being driven by a periodic interrupt, but the periodic flag (PF) bit is
still set at the periodic rate. PIE is not modified by any internal DS1689/DS1693 functions.
Bit 5: AIE (Alarm Interrupt Enable). This bit is a read/write bit which, when set to 1, permits the alarm
flag (AF) bit in Register C to assert
IRQ. An alarm interrupt occurs for each second that the three time
bytes equal the three alarm bytes, including a don’t care alarm code of binary 11XXXXXX. When the
AIE bit is set to 0, the AF bit does not initiate the
IRQ signal. The internal functions of the
DS1689/DS1693 do not affect the AIE bit.
Bit 4: UIE (Update-Ended Interrupt Enable). This bit is a read/write that enables the update-end flag
(UF) bit in Register C to assert
IRQ. The SET bit going high clears the UIE bit.
Bit 3: SQWE (Square-Wave Enable). When this bit is set to 1, a square-wave signal at the frequency
set by the rate-selection bits RS3–RS0 and the E32K bit is driven out on the SQW pin. When the SQWE
bit is set to 0, the SQW pin is held low. SQWE is a read/write bit.
Bit 2: DM (Data Mode). This bit indicates whether time and calendar information is in binary or BCD
format. The DM bit is set by the program to the appropriate format and can be read as required. This bit is
not modified by internal functions. A 1 in DM signifies binary data while a 0 in DM specifies Binary
Coded Decimal (BCD) data.
Bit 1: 24/12 (24/12 Control Bit). This bit establishes the format of the hours byte. A 1 indicates the 24-
hour mode and a 0 indicates the 12-hour mode. This bit is read/write.
Bit 0: DSE (Daylight Saving Enable). This bit is a read/write bit which enables two special updates
when DSE is set to 1. On the first Sunday in April the time increments from 1:59:59 am to 3:00:00 AM.
On the last Sunday in October when the time first reaches 1:59:59 AM it changes to 1:00:00 AM. These
special updates do not occur when the DSE bit is 0. This bit is not affected by internal functions.
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