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參數資料
| 型號： | DS1372U+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數： | 6/12頁 |
| 文件大小： | 0K |
| 描述： | IC BINARY COUNTER 32-BIT 8-USOP |
| 產品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 3,000 |
| 類型： | 二進制計數器 |
| 特點： | 警報器，方波輸出，監(jiān)視計時器 |
| 時間格式： | 二進制 |
| 數據格式： | 二進制 |
| 接口： | I²C，2 線串口 |
| 電源電壓： | 2.4 V ~ 5.5 V |
| 電壓 - 電源，電池： | 1.3 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應商設備封裝： | 8-uMAX |
| 包裝： | 帶卷 (TR) |
DS1372
_______________________________________________________________________________________
3
Note 1:
Limits at -40°C are guaranteed by design and not production tested.
Note 2:
All voltages are referenced to ground.
Note 3:
SCL clocking at maximum frequency = 400kHz.
Note 4:
Specified with I2C bus inactive, SCL = SDA = VCC.
Note 5:
Measured with a 32.768kHz crystal attached to the X1 and X2 pins.
Note 6:
The I2C minimum operating frequency is imposed by the requirement of timeout period.
Note 7:
The first clock pulse is generated after this period.
Note 8:
A device must internally provide a hold time of at least 300ns for the SDA signal (referred to as the VIHMIN of the SCL sig-
nal) to bridge the undefined region of the falling edge of SCL.
Note 9:
The maximum tHD:DAT must only be met if the device does not stretch the low period (tLOW) of the SCL signal.
Note 10: A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT
≥ 250ns must then be met.
This is automatically the case if the device does not stretch the low period of the SCL signal. If such a device does stretch
the low period of the SCL signal, it must output the next data bit to the SDA line tR(MAX) + tSU:DAT = 1000 + 250 = 1250ns
before the SCL line is released.
Note 11: CB = Total capacitance of one bus line in pF.
Note 12: The parameter tOSF is the period of time the oscillator must be stopped for the OSF flag to be set over the voltage range of
2.4V
≤ VCC ≤ VCC(MAX).
Note 13: The DS1372 can detect any single SCL clock held low longer than T_TIMEOUT (MIN). The I2C interface is in reset state and
can receive a new START condition when SCL is held low for at least T_TIMEOUT (MAX). Once the part detects this condi-
tion the SDA output is released. The oscillator must be running for this function to work.
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 2.4V to 5.5V, TA = -40°C to +85°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Fast mode
100
Data Setup Time (Note 10)
tSU:DAT
Standard mode
250
ns
Fast mode
20 +
0.1CB
300
Rise Time of SDA and SCL
Signals (Note 11)
tR
Standard mode
20 +
0.1CB
1000
ns
Fast mode
20 +
0.1CB
300
Fall Time of SDA and SCL Signals
(Note 11)
tF
Standard mode
20 +
0.1CB
300
ns
Fast mode
0.6
Setup Time for STOP Condition
tSU:STO
Standard mode
4.0
μs
Capacitive Load for Each Bus
Line (Note 11)
CB
400
pF
I/O Capacitance
CI/O
10
pF
SCL Spike Suppresion
TSP
30
ns
Oscillator Stop Flag (OSF) Delay
(Note 12)
tOSF
100
ms
Timeout Interval (Note 13)
T_TIMEOUT
25
35
ms
CRYSTAL SPECIFICATIONS
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
Nominal Frequency
fO
32.768
kHz
Capacitive Load
CL
12.5
pF
Equivalent Series Resistance
ESR
50
k
I2C, 32-Bit, Binary Counter Clock with 64-Bit ID
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